完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 阮桂棋 | en_US |
dc.contributor.author | Kuei-Chi Juan | en_US |
dc.contributor.author | 張俊彥 | en_US |
dc.contributor.author | Chun-Yen Chang | en_US |
dc.date.accessioned | 2014-12-12T02:12:11Z | - |
dc.date.available | 2014-12-12T02:12:11Z | - |
dc.date.issued | 1993 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT820430056 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/58056 | - |
dc.description.abstract | P型閘極P型金氧半元件中之硼擴散至氧化層效應,可以用多晶矽閘極予以 抑制.除此之外,在多晶矽閘極結構中的界面,可以進一步提高硼穿透所需 克服的位能障.應用多晶矽於閘極的上層,顯示出比較小的臨界電壓平移 值,較小的電子受陷速率,比較平滑的閘極表面形態和較大的崩潰電荷.在 多晶矽沉積後加上熱回火,硼穿透效應和氧化層品質可以同時達到改善的 目的. The effect of boron diffusion through the thin oxide in p+- gate PMOS devices can be suppressed by using an amorphous-Si gate. In addition, the interface in amorphous-Si gate structure can further increase the barrier for boron penetration. The use of amorphous-Si as the upper-layer gate exhibits a smaller flatband voltage shift, a less electron trapping rate, a more smooth gate surface morphology and a larger charge-to- breakdown. By thermal annealing after amorphous-Si deposition, an improvement both in boron penetration and gate oxide quality can be achieved simultaneously. | zh_TW |
dc.language.iso | en_US | en_US |
dc.subject | 多晶矽 | zh_TW |
dc.subject | Amorphous-Si | en_US |
dc.title | 不同的閘極微結構對於P型複晶閘極P型金氧半電容的硼穿透效應之研究 | zh_TW |
dc.title | Boron Penetration in Different Gate Microstructures of P+ Poly- Gate PMOS Capacitors | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |