BiCMOS 非整數除頻器

Abstract

本論文在描述一個射頻BiCMOS非整數除頻器的設計, 此除頻器是由一個三 階史格瑪調節器和一個多係數的除頻器所組成。非整數除頻器允許鎖相迴 路器能夠同時具備高解析度與快速換頻的功能, 藉由史格瑪調節的雜訊變 形的運用，非整數除頻所產生的相位雜訊可被濾除, 此鎖相迴路的最小頻 道間距是參考頻率的二千分之一, 低頻的相位雜訊的功率密度則比直流 低140dB多係數除頻器使用一微米BiCMOS製程, 它同時具備高速與低功率 消耗的特色，在攝氏125 度下, 此除頻器最高輸入頻率是 1.2GHz , 除頻 比率由 64 至 95 , 主要功率消耗來自雙載子電路, 而它的電流消耗是 68mA, 為了降低從第一級至最後一級所產生累積的相位雜訊, 再同步電路 被發展出來 This thesis describes a radio-frequency BiCMOS fractional- N frequency divider which is composed of a third-order Sigma- Delta modulator and a multi-modulus divider. The fractional-N frequency divider allows a phase-locked loop(PLL) to achieve fine frequency resolution and fast switching time. Phase noise introduced by fractional-N division can be removed by the use of the noise-shaping concept of Sigma-Delta modulation. The frequency resolution of the PLL using the divider is fi/2000. At low frequencies, the power density of the quantization noise is 140dB lower than dc output. The multi-modulus divider is fabricated with 1.0um BiCMOS technology. It has the characteristics of high speed and low power. The maximal input frequency of the divider is 1.2GHz. The divide number of the divider is from 64 to 95. The main sources of power consumption are Bipolar circuits whose current consumption are 68mA. A resynchronous circuit is designed to reduce the phase noise caused by accumulated delays from the first stage to the last stage.