以高速排序器設計參數可程式化的高速循序解碼器

Abstract

本篇論文提出一個嶄新的循序解碼的演算法以及 VLSI 架構和電路設計， 它可以適用於數位通信當中長 Constraint Length 的循環碼。這個新的 演算法是以排序(Sorting)和路徑紀錄(Path Recording)的技術為基處。 透過排序，我們可以以一種很快的方式找到正確的路徑；而經由路徑紀錄 的方法，我們可以在不降低系統效能的前題下得到解碼後的資料。從許多 的模擬結果當中可以發現在適當的選擇排序器的深度以及長度，可以得到 較 Viterbi 好的增益。根據提出的高效率VLSI架構可以使這演算法以單 晶片的方式實現出來。在硬體上，高速的排序動作是使用修改的SCAM來完 成；並使用可移動的暫存器陣列來達到路徑紀錄(Path Recording)的目的 。藉由這可程式超大型積體電路的製做，不但在Cosntraint Length上的 限制可以打破，而且可以使資料處理的速度提高；有利於應用在高速、長 Constraint Length的通信場合。此晶片以0.8mm CMOS技術來製做，在50 MHz的時脈下可達到25MHz的解碼速率。 This paper presents a new sequential decoding algorithm, its VLSI architecture and circuit layout for long constraint length convolutional code design in digital communications. This new algorithm is based on both sorting and path recording techni -ques. By means of sorting, we can identify the correct path in a very fast way and then, by path recording, we can recover the bit sequence without degrading decoding performance. Simulation results show that by appropriately selecting sorter length and depth, better coding gain than that obtained from Viterbi decoder can be achieved. An efficient VLSI architecture for single-chip implementation of this algorithm is presented too. High-speed sorting operations are realized on a modified shiftable content address memory and the path recorder is implemented on shiftable register array. With this efficient architecture and programmable VLSI chip, not only the constraint length limit is released but also small latency and high throughput decoding is achievable, making it suitable for high-speed decoding of long constraint length. Based on a 0.8mm CMOS single poly double metal technology, 25MHz decoding rate can be obtained at a 50MHz clock rate.