高速互補金氧半八位元快閃式類比數位轉換器之設計

Abstract

本論文利用0.8微米且兩層複晶矽兩層金屬的互補式金氧半技術設計了一 個八位元快速類比轉換器。為了完成高速且低功率的快閃式類比數位轉換 器,一個創新的比較器電路於是被提出,並且在50百萬赫茲取樣下,它的功 率消耗低於0.8毫瓦。而其直流漂移補償技術只用於第一級放大器中。除 此之外,使用了輸入取樣網路和輸入漂移補償技術以達到取樣類比輸入訊 號及消除共模訊號限制。在這篇論文中已設計出高速[ 每秒50百萬取樣率 ],低功率消耗[小於300毫瓦]及晶片工作面積[1500微米乘2700微米]的類 比數位轉換器。 An 8-bit high-speed A/D converter is designed in a 0.8-um CMOS double-polysilicon and double-metal process technology. In order to achieve a high-speed low-power flash A/D converter, a new comparator circuit is proposed. When operated at 50MHz sampling rate the power dissiption is below 0.8mW. The offset cancellation is incorporated in the first sense amplifier. In addition, an input sampling network and input offset cancellation is used to sample the two analog inputs and cancel their common- mode voltage. A high-speed(50MS/s), low power consumption (under 300mW) and active die area (1.5mm*2.7mm) of A/D converter has been designed.