電腦繪圖著色加速器的設計與實現

Abstract

在本論文中, 我們提供了一個繪圖加速器(Raster Engine)來增進繪圖與 影像的執行 效能. 此加速器可分攤 50% 的CPU 的運算負載. 此外 , 若 是應用Phong 的近似法(Approximated Phong Method)做運算的話, CPU 的運算量更 可減少原來的 89%. 在 RE 的設計技巧中, 我們使用了改良 的數位差分 分析式, 二層的管線化與餘琁值N次方的恆定時間計算法. 本 加速器共提供了三種運算模式: Gouraud, Phong 與 composition.由模擬 的結果顯示, 此系統運算頻率是 50MHz. 所以, 在 Gouraud與 composition 的運算模式下, 像素的更新速率是 6M/sec; 而在 Phong 的 運算模式下, 像素的更新速率是 3M/sec. 我們使用工研院電通所提供的 0.8 um, CMOS 的細胞庫來實現. 此加速器大約包含了22K的邏輯閘. 它的 大小約是 7684.5 um * 7444.8 um. 這顆IC將由TSMC以SPDM的技術製造. A Raster Engine( RE ) is designed and implemented to improve the performance of computer graphics and image composition. The RE hardware can release more than 50% CPU loads. Furthermore, if the approximated Phong method which is new proposed is 89% CPU operations are reduced. As the features of this design, the techniques including modified digitral differentail analyser (modified DDA), 2-level pipeline, and constant execution time for calculating cos^n\theta, are proposed in RE. Three operation modes: Gouraud, Phong and composition are incorporated in RE. The simulation results show that the system can operate up to 50MHz. As the result, the pixel update rate is 6M/sec for Gouraud shading and composition, and 3M/sec for Phong shading. The gate count of this chip is about 22K, and the die size is 7684.5um * 7444.8um. This chip is designed and implemented by using ITRI/CCL 0.8um CMOS cell library, and it will be fabricated by SPDM technology in TSMC.