取樣保持電路中電荷注入效應的分析與控制

Abstract

隨著資料轉換系統的日益進步，對取樣保持電路速度與精確度的要求也愈 來愈高，在金氧半取樣保持電路中影響其解析度最甚者為電荷注入效應． 在本篇論文□，我們對金氧半電晶體電荷注入效應做分析，並根據此分析 ，設計了兩種高速高精確度並且對電荷注入效應具有相當免疫力的取樣保 持電路．此兩種電路皆以 0.8微米雙層複晶矽雙層金屬製程技術來設計． 其性能已經 Hspice 電路模擬軟體及實驗晶片的量測驗證．模擬結果顯示 此兩種電路的解析度可達 9位元．於本論文中亦設計並分析了一個高速的 運算放大器，它可使開迴路取樣保持電路操作在85百萬赫茲的取樣速度， 和使閉迴路取樣保持電路操作在50百萬赫茲的取樣速度．兩性能評估皆已 考慮實際應用於類比－數位放大器時的電容負載． As data conversion systems continue to improve in speed and resolution, increasing demands are placed on the performance of high speed, high solution sample-and-hold circuits. One factor that degenerates seriously the resolution of the MOS samle-and- hold is the input-dependent charge injection. In this thesis, analysis is placed on the charge injection phenomenon. Based on this thesis, two high-speed sample-ahd-hold with good immunity against input dependent charge injection are designed and analyzed. Both the circuits have been implemented in a 0.8um double-poly double-metal CMOS technology. The operation and performance of the sample-and- hold circuits have been verified through Hspice simulation and test chip measurement. Simulation results show that the resolution of both circuits are at least 9-bits. A high-speed operational amplifier is also designed and analyzed. Based on this new amplifier, the sampling rate can be raised up to 83MHz for open-loop sample-and-hold and 50MHz for closed-loop sample-and-hold, all considering the capacirive loading when utilized in the analog-to-digital converter.