離散弦轉換之超大型積體電路陣列設計

Abstract

本論文主要針對離散弦轉換之超大型積體電路陣列設計提出一個有系統的 設計方法，此方法分別從演算法、硬體架構及實現方式等三方面加以分析 考量，採取迴旋列式演算法、心脈式陣列架構與以記憶體為結構基礎之實 現。利用此項方法所設計的陣列，比傳統利用乘法器之心脈式陣列及近年 來流行的分散式算術為基礎之陣列更能節省硬體成本。此外，本論文亦推 導了一個針對多維離散哈特利轉換的新列式，利用此列式可以避免以傳統 方法設計所帶來的額外代價。 This dissertation presents a systematic approach to design VLSI arrays for the discrete sinusoidal transforms. Considering from the aspects of algorithm, architecture, and implementation, the presented approach adopts the cyclic convolution formulation, systolic array realization, and memory-based implementation. Using the presented approach can yield VLSI array designs which are more efficient in hardware than the conventional systolic arrays based on multipliers and the distributed arithmetic architectures. In addition, in this dissertation, we also develop a new formulation for the multi-dimensional discrete Hartley transform such that we can avoid the undesirable overhead in the hardware designs resulted from the conventional design approach.