一種存在於互補式超大型積體電路的雙橫向鎖住行為之探討

Abstract

本論文內容詳述一種新型式的鎖住效應 (LATCH-UP) 行為。此種鎖住效 應, 有異於傳統的鎖住效應現象, 而呈現一種類似二級交流轉換器 (DIAC-SIMILAR)之特性曲線; 但又非真正具有 DIAC 相同之結構。此一 DIAC0SIMILAR 行為可發生於積體電路中之兩輸入 (INPUT) 或輸出 (OUTPUT)接腳間。而非如傳統鎖住效應發生於電源接腳 (VDD)及接地接 腳 (VSS)間。經由元件之分析, 我們探討了此一新型鎖住效應之觸發原 理, 並加以各種實驗之驗證。而元件模式 (DEVICE MODELING)之建立,也 在審慎且佐以實驗結果驗證下完成。此模式命名為 ─ 修飾型混合要素模 式 (THE MODIFIED LUMPED ELEMENT MODEL)。經過元件之分析及模式推導 後, 如何於互補式金氧半積體電路(CMOS)的靜電釋放 (ESD)保護電路中 或 CMOS 的輸出緩衝線路 (OUTPUT BUFFER)中, 于以最佳化, 來避免此一 新型式鎖住效應對產品的功能或可靠性上之破壞, 亦在本論文中被詳細提 及。本論文之研究成果, 對未來低功率超大型積體電路之發展, 具相當之 重要性。尤其對 OUTPUT BUFFER 雜音之困擾 , 經過透徹瞭解後能夠得所 應對。 The results of serial studies on the behavior of bilateral latch-up in CMOS protection circuits are presented. Latch-up and ESD problems are two major factors that degrade VLSI pro- duct reliability. A new latch-up phenomenon showing symmetrical diac-similar I-V characteristics has been discovered recently. Electrical measurements show that a diac-similar parasitic semi- conductor-controlled-rectifier (SCR) device can exist between two adjacent ESD protection circuits or output buffers. The SCR consists of two parasitic PNPN paths and can easily induce a localized SCR latch-up between two adjacent input or output ter- minals. This is a new bilateral latch-up path between two ad- jacent input and output pins. A new latch-up failure mode due to this diac-similar structure, which creates a bilateral path during the temperature humidity bias (THB) testing discussed. The failure mode can be observed and verified by cross section techniques or latch-up triggering test experimentation. Some suggestions regarding how to improve this diac-similar latch-up degradation are proposed. Advanced analyses and modeling are also presented in this paper. The modified lumped element model explains this diac-similar latch- up phenomenon. Bilateral latch up self-triggering resulting from series resistance or series inductance on Vdd or Vss is discussed. Optimizing the layout and design of output buffers to improve product performance and re- liability is also recommended. The studies on the behavior of bilateral latch up in CMOS protection circuits are more important since low power applications are becoming the future trends.