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dc.contributor.authorCheng, P. L.en_US
dc.contributor.authorLiao, C. I.en_US
dc.contributor.authorWu, H. R.en_US
dc.contributor.authorChen, Y. C.en_US
dc.contributor.authorChien, C. C.en_US
dc.contributor.authorYang, C. L.en_US
dc.contributor.authorTzou, S. F.en_US
dc.contributor.authorTang, J.en_US
dc.contributor.authorKodali, R.en_US
dc.contributor.authorWashington, L.en_US
dc.contributor.authorCho, Y.en_US
dc.contributor.authorChang, V. C.en_US
dc.contributor.authorFu, T.en_US
dc.contributor.authorHsu, W. S.en_US
dc.date.accessioned2014-12-08T15:07:23Z-
dc.date.available2014-12-08T15:07:23Z-
dc.date.issued2007-01-01en_US
dc.identifier.issn0268-1242en_US
dc.identifier.urihttp://dx.doi.org/10.1088/0268-1242/22/1/S33en_US
dc.identifier.urihttp://hdl.handle.net/11536/5824-
dc.description.abstractSeveral dry and wet surface treatment methods are explored for a selective SiGe epitaxial film used to fabricate embedded SiGe pMOSFETs. Pre-clean conditions for the device wafers used in this study were limited by a realistic CMOS process window with tight thermal and chemical budgets due to dopant diffusion and hardmask erosion concerns. The effectiveness of these pre-clean methods is evaluated by SiGe epitaxial film quality and SIMS profiles of key residual contaminants such as C and O at the SiGe-Si substrate interface. As an effective low-temperature dry surface treatment, chemical bake in HCl/H-2 at temperature below 800 degrees C is found to reduce interface C and O peak concentrations by an order of magnitude. Wet clean in multiple cycles of DIW-O-3 (ozonated water), SC1 and diluted HF (DHF) is also presented to prepare epitaxial growth surfaces with accumulated damage and chemical residues from previous process steps. SiGe epitaxial film morphology is also observed to improve by increasing DHF clean time. For further improvement of film quality on the most difficult surfaces, Si seed layer was employed to initiate SiGe film nucleation and yield smooth film growth.en_US
dc.language.isoen_USen_US
dc.titleEffective surface treatments for selective epitaxial SiGe growth in locally strained pMOSFETsen_US
dc.typeArticle; Proceedings Paperen_US
dc.identifier.doi10.1088/0268-1242/22/1/S33en_US
dc.identifier.journalSEMICONDUCTOR SCIENCE AND TECHNOLOGYen_US
dc.citation.volume22en_US
dc.citation.issue1en_US
dc.citation.spageS140en_US
dc.citation.epageS143en_US
dc.contributor.department交大名義發表zh_TW
dc.contributor.departmentNational Chiao Tung Universityen_US
dc.identifier.wosnumberWOS:000243752500034-
Appears in Collections:Conferences Paper


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