新的二維熱載模擬技術及在次微米金氧半場效電晶體和快閃記憶體分析上的應用

Abstract

本論文中，我們提出一些新且高效率的模式，以分析短通道金氧半場效電晶體的熱載子效應（hot carrier effects）。所有發展出的模式皆建構在SUMMOS二維模擬器中，以執行元件的特性分析。在第一章中，我們先說明發展熱載子模式的動機，同時簡單地描述SUMMOS二維模擬器以及元件摻雜分佈的粹取方法。 第二章中，我們發展了一個新的撞擊游離（impact ionization）模式。此模式考慮到熱載子在n-型通道金氧半場效電晶體界面的運動。我們的模式將非局部效應（non-local effect）轉換成用載子運動路徑和電場分佈來表示的平均路徑（mean-free-path）公式。利用這樣的方式，撞擊游離所產生的電子-電洞對就不會局限於最大電場處，因而反應出真正的物理現象。利用這樣的撞擊游離模式，二維SUMMOS模擬器已能正確地計算元件的基片電流（substrate current）。測試的元件有傳統（conventional）和淺摻雜（LDD）n-型通道金氧半場效電晶體，且涵蓋了各種不同的氧化層厚度、通道長度以及大範圍變化的端點壓。計算的結果與實驗值非常吻合。 第三章中，我們發展出一個有效且正確的二維閘極電流（gate current）模式，以模擬短通道金氧半場效電晶體的熱載子效應。我們修改了Ning等人提出的一維基板射入（substrate injection）機率，把通道熱電子所增加的射入機率加以考慮，以模擬元件的二維效應。增加的機率是用載子的運動路徑以及其功率密度的流程來表示，同時也利用模擬所得的汲極、基片、閘極電流與實驗元件特性來確認其正確性。我們的實驗元件為n-型通道金氧半場效電晶體，其通道長度由0.64微米至0.34微米，氧化層厚度為200埃。除了熱載子射入機率的模式發展外，因熱電子射入而產生的界面陷阱（Si/SiO2 interface traps）及其對金氧半場效電晶體汲極、基片、閘極電流的影響也一併考慮到。這些在界面產生的電子陷阱會增強撞擊游離速率，加速元件的衰退，但是卻會阻擋電子持續地射入氧化層。為了印證模式的正確性，我們採用了一個通道長度為0.45微米而氧化層厚度為100埃的短通道金氧半場效電晶體作為測試元件。由SUMMOS模擬出的基片電流、閘極電流及汲極電流的衰退，都與實驗值非常吻合。不僅如此，由模式粹取出的界面陷阱空間分佈情形也與由電荷幫浦電流（charge pumping current）測得的結果相互印證。與其他在文獻上所發表過閘極電流的模式比較起來，我們模式最大的特點在於簡單而且正確。它可以很輕易地放入目前工業界使用的各種二維元件模擬器。 在第四章中，我們將發展出的閘極電流模式應用到n-型通道快閃可程式記憶體（Flash EEPROM）的特性分析。只需要考慮在浮閘（floating gate）上的貯存存電荷邊界條件（charge boundary condition），我們原先所發展的閘極電流模式就可用來分析n-型通道快閃可程式記憶體的“寫”（write）動作。同樣地，我們也利用實驗n-型通道快閃可程式記憶體在不同通道長度及不同偏壓狀態下，所得之臨界電壓（threshold voltage）和“寫”時間之間的變化來驗證模式的正確性。模擬的結果與實驗值十分吻合。除了與實驗值比較，我們也用模擬的方式探究了元件摻雜分佈變化如何地影響到快閃可程式記憶體寫的速度。模擬的結果可作為元件設計者的參考依據。此外，當快閃可程式記憶體一直反覆地寫入，在氧化層內的電子陷阱則不斷地累積，因而造成快閃可程式記憶體可靠性的問題。模擬的結果顯示了很明顯的臨界電壓偏移縮減的效果。而且這樣的縮減會隨著氧化層電子陷阱的累積不斷地惡化。由此，我們的SUMMOS模擬器亦可應用到快閃可程式記憶體可靠性的預估。 最後，在第五章中，我們作一總結並提出在此研究領域中可延伸探索的方向。

In this thesis, several new and efficient macroscopic models are presented to characterize the hot-carrier effects of short channel MOSFETs. All the developed models have been implemented into a submicron MOS two-dimensional simulator (SUMMOS) for device characterization. In chapter l, the motivation to develop the hot-carrier effect concerned with the macroscopic models is addressed. A brief description of the SUMMOS simulator and the extraction proce-dure for device doping profile are given. In chapter 2, a new macroscopic impact ionization model for submicrometer n-MOSFETs has been developed by considering the important physical features of hot-carrier motion near the Si/SiO2 interface. The non-local effects have been transformed into our carrier motion depth-and field-dependent meanfree-path formulation so that the impact ionization events will not localize at the maximum electric field. This impact ionization model has been implemented into the SUMMOS 2-D simulator and verified by the experimental substrate current. It is shown that the calculated substrate current matches experimental results very well for both conventional and LDD n-MOSFETs with different oxide thicknesses, different effective channel lengths under wide ranges of gate, drain, and back-gate biases. In chapter 3, an efficient and accurate 2-D phenomenological gate current model is developed to simulate the hot-electron effects on short-channel n-MOSFETs. The 1-D injection probability used by Ning et al. for substrate injection has been further modified by considering the channel hot-electron enhanced injection probability in terms of the actual carrier current path and its power density flow. This new injection probability has been well verified by the simulated drain, substrate, and gate currents. Quite good agreements with the experimental results have been obtained for the n-channel MOSFETs with different effective channel lengths ranging from 0.64m to 0.34m and the oxide thickness of 200A. In addition to the injection probability, the hot-electron-injection-in-duced Si/SiO2 interface-trap generation and its effects on MOSFET drain, substrate, and gate currents have also been taken into consideration. It is shown that the generated electron traps at the Si/SiO2 interface enhance both the impact ionization rate and the degradation of MOSFET characteristics but retard the injection probability of hot electrons into the gate oxide. The spatial distribution of the generated Si/SiO2 interface traps calculated by our model has been well verified by the charge pumpimg measurement. Furthermore the simulated substrate current, gate current, and degradation of drain current are in good agreement with the experimental results of a short-channel n-MOSFET with the oxide thickness of 100A and the effective channel length of 0.45m for wide ranges of drain and gate biases. Compared with other published gate current models for short-channel MOSFETs, the most important features of our developed gate currevt model are simple, accurate, and easy to incorporate with existiong drift-diffu-sion 2-D device simulator. In chapter 4, some applications of our developed models to characterize the submicrometer n-channel flash EEPROM are proposed. With considering an extra charge boundary condition on the floating gate, this well-established gate current model has been applied to characterize n-channel flash EEPROM writing. Comparisons with experimental EEPROM writing has been made, and quite good agreements have been obtained for test devices with different channel lengths ranging from 0.8um to 0.5um under different applied biases. The deviation on writing speed caused by the fluctuation of device doping profile has been studied. This can be used as a guideline for flash EEPROM device design. Moreover, computer simulation of the reliability problem caused by electron traps in the oxide layer has also been performed to characterize the endurance of flash EEPROM. Apparent narrowing of threshold-voltage shift has been observed when the oxide electron traps increase due to repeated writing operation. In summary, the major contributions of this thesis as well as the suggested future works are given in chapter 5.