完整後設資料紀錄
DC 欄位語言
dc.contributor.author李國禎en_US
dc.contributor.authorK. J. Leeen_US
dc.contributor.author鍾淑馨en_US
dc.contributor.authorS. H. Chungen_US
dc.date.accessioned2014-12-12T02:13:06Z-
dc.date.available2014-12-12T02:13:06Z-
dc.date.issued1994en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT830030024en_US
dc.identifier.urihttp://hdl.handle.net/11536/58787-
dc.description.abstract目前國內晶圓製造業正處於景氣狀態,故需極大化產能以提高利潤,但產 能的提昇,卻造成在製品量增加及生產週期時間增長等不良後果。因此, 本文基於存貨控制(WIP Control)及平衡產出的理念,在權衡產出、在製 品量水準及生產週期時間三者關係之前題下,來發展晶圓製造系統之規劃 控制模式。基於時效性及規劃精確度的考量,本論文所提之模式共分為主 生產排程、細部排程及現場控制三個階段。此三階段係為層級式架構,各 階段有不同考量之目標,但較高層級之決策結果為較低層級之規劃目標。 本文在主生產排程階段所決定之理想在製品量水準,係考量欲產出之產品 組合及產出量而得之在製品量水準,因此主生產排程之規劃結果能確實達 成,此可由最後的驗證結果中看出。在細部排程階段則將主生產排程之產 出量和在製品量資訊細分成以層級通過(瓶頸資源作業之次數)為單位,因 此現場控制階段能以層級為核心,對產出量和在製品量作更精確的控確的 控制,對於改善系統的實際在製品量水準和實際生產週期時間,均有極佳 之成效。 The wafer fabrication is in the blooming state such that maximizing capacity utilization to promote profits is needed. However, the increasing capacity utilization rate may cause the results of large WIP quantities, long flow times,..., and etc. Based on the concepts of WIP control and output balancing, this thesis attends to develop the production planning model for wafer fabrication factories with consideration of the production rate, WIP level, and the flow times of products. This model is divided into three stages: master production schedule(MPS), detailed schedule, and shop floor control. These three stages construct a hierarchical relationship, that exists in the setting of objective for each stage. That is, accomplishing the planning output of the upper stage is the planning objective of a lower stage. The MPS stage considers the desired product mix and output volume to set the level of WIP in each planning period--4 weeks. Under the situation that the production mix, output volume, and WIP level are fixed, the flow time thus can be controlled in the shop floor control stage to satisfy the MPS. The detailed scheduling stage then plans the work that should be done in a week. It uses the number of times passed through the bottleneck machines(number of layers) to express the status of WIP and the output.As a result, the shop floor control stages controls the output and WIP by layer.The flow time, and the WIP level can thus be actually controlled such that the MPS can be achieved.zh_TW
dc.language.isozh_TWen_US
dc.subject晶圓製造;層級zh_TW
dc.subjectWafer fabrication;layeren_US
dc.title晶圓製造廠生產規劃模式之構建zh_TW
dc.titleThe Construction of Production Planning System for Wafer Fabrication Factoriesen_US
dc.typeThesisen_US
dc.contributor.department工業工程與管理學系zh_TW
顯示於類別:畢業論文