良率分析應用於動態隨機存取記憶體中區域分割及修復電路設計之研究

Abstract

如何有效的提升IC產品良率，以達到經濟效益，是積體電路產業最重要的 課題之一。在提升動態隨機存取記憶體良率方面，除了改善製程與技術以 減少缺陷的發生之外，晶片上電路設計的方式亦是重要的因素。一般而言 ，晶片上分成若干個一模一樣的區域，每個區域內會設計若干個備用元件 。這些區域分割及備用元件數都會影響到晶片的良率及成本，因此如何建 立一個能夠分析區域分割及備用元件數之良率模式是非常重要的。本研究 是以目前最普遍為大家所採用的負二項良率模式為基礎，根據 16百萬位 元DRAM晶片之結構型態，建立一個能夠分析區域分割及備用元件數之良率 模式。透過觀察16百萬位元DRAM晶片之bitmap，得到各修復電路計劃的資 料，再用這些資料來推導負二項良率模式中的參數，進而提出16百萬位元 DRAM晶片之最適區域分割及備用元件數的建議，使晶片的良率達到既訂水 準。此外，更可依此進一步發展出一個預測16百萬位元以上DRAM晶片之最 適區域分割及備用元件數，並預估其良率水準。 With the increase in memory density, large chip size, small pattern size, and complicated cell structure, achieving high yield is hindered. Therefore, it is an important issue surrounding the IC industrial to maintain an effectively high yield. With an increasing yield of DRAM's, it is also an important factor that the design of circuits in wafer improves the manufacturing process and reduces defects. In general, the typical chip architecture of DRAM's is divided into various sections. The spare elements are prepared in each section. The section division and number of spare elements effectively impact yield and the cost of chips. Therefore, it is very important to establish a yield model which can accurately analyze section division and the number of spare elements. The yield model employed analyze section division and the number of spare elements based on negative bynomial yield model. This yield model is established by the architecture of 16 Mb DRAM's. The data of redundancy scheme is obtained by observing bitmap of 16 Mb DRAM's and employed to compute the unknown parameters of the negative bynomial yield model. It is proposed that the optimized section division and redundancy scheme of 16 Mb DRAM' s can reach the decided yield model.