30奈米DRAM儲存節點連接之良率改善

Abstract

積體電路（integrated circuit, IC）的製造，從設計、晶圓製程、封裝到測試等，是十分精密且複雜的過程。而所謂的晶圓製程主要是指從晶片投入到晶片測試間的製造過程，其中微影製程是晶圓製程中最關鍵的步驟，每個IC圖形皆由微影製程決定；而元件的最小線寬，也是受限於微影製程的解析能力。隨著半導體製程技術的演進，積體電路的元件線寬越來越小，疊對偏移的要求也越來越嚴謹。而曝光機台本身的能力及穩定度是影響疊對偏移的主因，次要則是底層結構影響曝光時自動對焦的行為。 本論文在研究如何改善動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）的良率，研究對象為30奈米後段製程的儲存節點連接接墊（Storage Node PAD，SP)，使用的微影機台為ASML XT1950Hi浸潤式掃描式曝光機。改善方式有1.疊對誤差評估(wafer induce shift, WIS)；2.臨界尺寸變化評估(critical dimension, CD)；3.蝕刻參數調整；4.薄膜參數調整。經由長期實驗觀察後，使用上述四種方式良率皆能有所改善，其中疊對誤差與臨界尺寸變化為主要改善方式，量化後統計可提升良率2~4％，並已將其套用在FAB生產線上提升良率。

The process of manufacturing an integrated circuit (IC), including IC design, wafer fabrication, packaging and final testing, is an extremely precise and complicated process. The wafer fabrication processes consist of the processes from the wafer input, semiconducting processing to wafer test and yield. Lithography is the most important step in the semiconducting processing because each IC pattern is determined by the lithography process. Moreover, the limitation of the linewidth of the device is also determined by the resolution of the lithography system. The critical dimension of the IC devices is getting smaller and smaller as the semiconducting processing progresses and more rigorous requirement of the overlay shift margin is needed. The capability and stability of the exposure machine (scanner or stepper) are the primary factors to affect the overlay shift. Besides, the overlay shift is also affected by the auto focusing due to the structure of under-layer during exposure. In the present work, we study how to increase the yield of DRAM devices by improving the 30 nm Storage Node Contact PAD at backend process step. The lithography and exposure machine used in this study is ASML XT-1950Hi (Immersion Scanner). Four methods include (1) overlay shift evaluate（wafer induce shift, WIS, (2) change critical dimension (CD), (3) adjust etch process parameter and (4) adjust thin film parameter are tested. After long-term experimental observation and measurements, we find that the overlay shift and the critical dimension are the dominant factors to affect the performance. We have already applied these results on FAB production line and promoted the yield rate 2~4%.