x86超純量處理器內暫存器重命名之研究

Abstract

超純量處理器藉由發出多個指令到多個功能單元，以便能同時使用這些功 能單元。然而由程式內分歧障礙及資料相依關係使得超純量處理器無法充 分發揮其應有效能。由分歧障礙及資料相依關係所引起之負面影響，可藉 由硬體或軟體方式重排指令順序而減低。暫存器重命名是一種提供重序原 指令順序有效的方法。暫存器重命名技術藉由消除指令間資料逆相依及資 料輸出相依，以讓更多彼此無關指令在超純量處理下同時執行。因 x86處 理器比典型RISC(精簡指令處理器)有較少的一般用途暫存器，故這些暫存 器在程式執行時將使用的更頻繁。因此藉由暫存器重命名技術以揭露更多 指令間的平行度是必要的。由於在這些處理器內的32位元暫存器可再分成 數個16位元或 8位元的彼此獨立暫存器，因此使得暫存器重命名技術不易 於在此種處理器上使用。在本論文中，我們提出兩種使用於 x86超純量處 理器內暫存器重命名硬體方法，並在擁有保留表(reservation stations) 及重序緩衝器(reorder buffer)的 x86超純量處理器上評估這兩種方法的 效能。第一種暫存器重命名方法是個較直覺的方法，但其硬體成本使它較 不合宜；第二種則為降低硬體成本而設計，但其效能可能不如第一種方法 。模擬結果顯示第二種方法在維持第一種方法百分之九十九之效能的狀況 下，使硬體線路儘量簡單。 Superscalar processors exploit the concurrent use of multiple functional units by issuing multiple instructions to these functional units. However, they still suffer from two impediments: branch hazards and data dependencies. The penalties caused by them in the processor can be minimized by rearranging the instruction sequence with a hardware or software approach. And register renaming is a very effective technique in providing the freedom for moving instructions around in the original instruction sequence. Register renaming mechanism removes the anti- and output dependencies between instructions to allow more independent instructions to execute in parallel in superscalar processing. In x86 processors, there are fewer general-purpose registers than those in a typical RISC processor, and reusing of the registers in a program is expected to be more frequent. Therefore, renaming the registers to uncover the instruction parallelism is needed. However, a 32-bit extended register can be further divided into 16- or 8-bit independent registers in these processors, which makes renaming very difficult. In this thesis, we propose two renaming hardware schemes in an x86 superscalar processor, and evaluate them on an aggressive superscalar processor machine model with reservation stations and a reorder buffer. The first of the two renaming schemes is an intuitive design, whose hardware cost may make it less desirable; and the second is to aim at reducing the hardware cost, with possibly deteriorated performance. Simulation results show that the second scheme can reduce the hardware cost while retaining about 99 percent of the performance from the register renaming by the first scheme.