非同步傳輸網路之高速交換鍵設計及實現

Abstract

在本論文中，我們提出一個適用於寬頻整合服務數位網路的高速及高輸出 率的非同步傳輸網路交換鍵。為了獲得較好的效能，此交換鍵採用多重匯 流排架構。此交換鍵由兩大模組組成：輸入貯列控制及小封包傳輸控制。 第一個模組負責輸入端流量及輸入端緩衝區的管理，第二個模組負責裁決 小封包傳輸的優先權。每一個輸入端可以同時傳送小封包，並且透過匯流 排同時直接將小封包傳送到輸出端。每一個輸入小封包透過路徑表得到輸 出端的位置，而這個路徑表是以隨機存取記憶體實現，它可以存放單點播 送、全面播送及多點播送的輸出端位置。我們利用輸入端緩衝區來避免小 封包遺失，並且採用一個複雜度為log n的平行比較演算法來解決輸出擁 塞的情況，其中n代表輸入端的數目。平行比較演算法是用以找出具有最 大權重的輸入端，而此輸入端將取得傳送小封包的最高優先權。因為在輸 入端傳送小封包到輸出端之前，可能的輸出端擁塞已經被解決，因此我們 所提出的交換鍵不會有輸出端擁塞的情況產生。採用多重匯流排架構，可 使處理全面播送或多點播送如同單點播送，並不需要特別處理。從輸入端 傳送小封包到輸出端總共只需花log n個時序週期。雖然我們所提出的交 換鍵採用匯流排架構，它的效率可以符合非同步傳輸網路的需求，同時也 不受限於輸入端數目的多寡。在這種情況下，我們提出的方法比其它同樣 採用匯流排架構的方法好。利用標準硬體描述語言所做的模擬結果可以驗 證此交換鍵的機能，其合成的結果也可以用來評估此交換鍵的延遲時間和 面積。分析及實驗結果都證明我們所提出的非同步傳輸交換鍵架構可以滿 足高速及高輸出率的需求。 In this thesis, we propose a high speed and high throughput Asynchronous Transfer Mode (ATM) switch architecture for broadband ISDN (B-ISDN) networks. The ATM switch is based on a multiple bus structure to get the best performance. The ATM switch consists of two basic modules: input queue control and cell transmission control. The first module handles input traffic and input buffers, while the second module arbitrates the piority of cell transfer. All input ports can transmit a respective cell simultaneously, and the cells are transmitted to output ports in parallel. The destination of each input cell is obtained from a routing table. The routing table is implemented by a random access memory, which may contains single cast, broadcast and multicast addresses. We employ input buffers to avoid cell loss and resolve output congestion by using a parallel comparison algorithm with log n complexity, where n is the number of input ports. The algorithm is to find out an input with the largest weight, and the selected input will get the highest priority to transmit a cell. Since output contention is resolved before cells are transmitted to output ports, this switch is thus free of output congestion. Because we use a bus structure to implement the switch, it results in easiness in handling broadcast/multicast traffic as well as single cast traffic. The switching time from an input port to an output port just takes 2+log n clock cycles. Although our switch is based on the bus structure, its performance can meet the ATM requirements and is not limited by the number of input ports. In this aspect, our approach is better than other approaches using the bus structure. Simulation with VHDL has been performed to verify the functionalities of the proposed switch. Synthesis has also been conducted to evaluate delay and area. The analysis and experimental results demonstrate that our ATM switch architecture can meet high speed and high throughput requirements.