次微米元件之製程與分析

Abstract

在本論文中，首先運用鈀金屬膜與金屬矽化物膜來當做佈植障礙層，於低 溫中製成P+N 淺接面。理想因子約1.05，漏電流密度數奈安 /平方公分的 淺接面可於500度C與550度C的低溫製程中被研製成功。運用金屬膜與金屬 矽化物當佈植障礙層亦可製成特性良好的N+P接面。另外，佈植磷離子於 金屬膜或金屬矽化物膜均能增進其高溫穩定性，並且發現與佈植能量沒有 關係。運用佈植BF2+離子於1500埃複晶矽中經後續退火，可得漏電流密 度1奈安/平方公分,接面深度0.05微米的接面。運用佈植雜質磷於複晶矽 法可製成特性良好的N+P淺接面。即使在很高的佈植能量條件下，亦可 於900度C退火後得到特性良好的接面。然而，只有高劑量佈植，才能 於800度C得到特性良好的接面。 Good Pd-silicided p+n diodes with ideality factor of about 1.05 and leakage current of a few nA/cm2 could be obtained under annealing temperatures as low as 500(C and 550(C for the ITM and ITS samples. Excellent n+p diodes have been fabricated using Pd and Pd2Si as the implantation barrier. Furthermore, implantation of phosphorus ions into silicide films is found to effectively stabilize silicide films from degradation, both in ITM and ITS schemes. No correlation between implantation energy and silicide degradation temperature was found. By properly implanting BF2+ ions into thin poly-Si films (1500 A) and subsequent annealing, the non-silicided ITP p+n junction diodes with a leakage of 1 nA/cm2 and a junction depth of about 0.05um have been achieved. Excellent ITP n+p junctions can be obtained for annealing temperatures at 900C or above even for the high energy phosphorus implantation cases, which introduces severe damages in silicon substrate. However, only the high dose implanted samples can achieve good junction characteristics after a 800C annealing.