一個工作在２伏特２Ｇ赫茲之鎖相迴路積體電路

Abstract

本篇論文描述２伏特２Ｇ赫茲的鎖相迴路，它包含相頻偵測器、電荷充式 濾波器、變頻振盪器和多係數除頻器。相頻偵測器比較兩個時脈輸入的相 位。可偵測的最小相位差是0.3ns。電荷充式濾波器將相頻偵測器的數位 式輸出轉成變頻振盪器所能接受的類比輸入訊號。電荷充式濾波器的輸出 電壓是正比於兩個時脈輸入的相位差。負電阻電感電容振盪器所能輸出的 頻率是從1.19GHz到2.35GHz。當多係數除頻器是經由調變所控制時，鎖相 迴路能同時穫得較微細的頻率解析和較短的交換時間。在125oC時係數除 頻器所能接受的最快輸入頻率是1.6 GHz。除數的大小是從64到126，其所 耗的電流是68mA。一個同步的電路是為了降低從第一級到最後一級因為傳 輸延遲所造成的相位雜訊而設計。這個鎖相迴路是架構在改良的電流式邏 輯而用1.0um BiCMOS製程製造。它能工作在2伏特且輸出頻率高達2GHz。 總消耗電流88.25mA。鎖相迴路的巨集模式將會被介紹而其捕捉的過程將 會用SPICE模擬。 This thesis describes a 2~V 2~GHz phase-locked loop (PLL) which is composed of a phase frequency detector, charge-pump filter, variable frequency oscillator (VFO) and a multi-modulus divider. The phase-frequency detector (PFD) compares the phase of the two clock inputs. The minimum phase difference that PFD can detects is 0.3ns. The charge-pump filter converts the sequential logic states of the PFD's outputs into analog signals which is suitable for controlling the VFO. The output voltage of charge-pump filter is linearly proportion to the phase error of the two clock inputs. The output frequency range of the negative resistance LC-tuned oscillator is from 1.19~GHz to 2.35~GHz. A multi-modulus frequency divider allows a PLL to achieve fine frequency resolution and fast switching time at the same time, when the multi-modulus divider is controlled by a sigma-delta modulation. The maximal input frequency of the multi-modulus divider is 1.6~GHz at $125~\DegC{}$. The divide number of the divider is from 64 to 126.The power consumption of multi-modulus divider is 68~mA.To reduce the phase noise caused by accumulated delays from the first stage to the last stage, A resynchronous circuit is designed. The PLL is fabricated with 1.0~um BiCMOS technology. Base on the improved current-mode logic (ICML), the PLL can operates under 2~V and the output frequency is up to 2~GHz. The total power consumption of PLL is 88.25~mA. The macromodel of the PLL will be introduced for simulation the lock process.