LMDS之本地振盪器研製

Abstract

本論文研究LMDS中本地振盪器之製作，利用混成式積體電路的製程與微帶線的電路結構，以乘頻式的鎖相方法製作類比式鎖相迴路，將訊號鎖定在6.525GHz後，並以倍頻電路，使輸出訊號頻率為13.05GHz。 文中說明鎖相迴路與FET倍頻電路的原理，並以此為設計之基礎。電路之量測結果在輸出端可得10dBm之13.05GHz訊號，其相位雜訊為-93dBc/Hz@10kHz offset，而6.525GHz訊號之壓制可與13.05GHz訊號相差20dB以上。

The thesis presents the design and fabrication of Local Oscillator for LMDS. The process of Hybrid Microwave Integrated Circuits (HMIC) and the structure of microstrip lines are applied in this design. The analog PLL is applying the method of frequency multiplication where the fundamental oscillator is phase locked at 6.525GHz. A FET frequency doubler obtains the signal at 13.05GHz. The thesis describes the theory of analog PLL and FET frequency doubler. The power of 13.05GHz source is 10dBm and the phase noise is –93dBc/Hz@offset 10kHz. The power suppression of 6.525GHz is above 20dB.