離散餘弦轉換之設計與製作

Abstract

離散餘弦轉換（DCT）及其反轉換在今日的各個數位聲音和影像的通訊標 準中負責使輸入資料的重覆資料減少（removal of redundancy in correlation）的角色，以使得其後的量化（Quantisation）與亂度編碼 Entropy Coding）等動作能有良好的壓縮效率。由於其運算量頗大，在實 際製作需要特別地考量。傳統上較為常用的方式為所謂「以唯讀記憶體為 主的分散式算術（ROM-Based Distributed Arithmetic）」架構，此作法 用在離散餘弦轉換及其反轉換的製作上需要相當大量的唯讀記憶體。本論 文提出了一種新的「以加法器為主的分散式算術（Adder-Based DA）」架 構，使用電晶體數與所佔面積較少的加法器代替傳統架構中的唯讀記憶體 ，以減少整體離散餘弦轉換或反轉換在晶片製作上所需要的成本。我們亦 實際以工研院電通所的標準元件（Standard Cells）設計並製作了二維反 離散餘弦轉換的晶片，該晶片的核心部分（core）只用去 16 平方毫米， 且在 VERILOG 的模擬達到每秒 98 佰萬像素的速度。 Discrete Cosine Transform (DCT) is now used in many communication standards for the removal of redundancies of correlation in random sequences. A random sequence with less correlation could be well compressed after quantisation and entropy coding. Since DCT and its inverse (IDCT) cost much computation power, the design of DCT or IDCT is important in overall system consideration. Traditionally, ROM-Based Distributed Arithmetic (DA) architecture has been used in many commercial systems. Since ROMs cost much area in ROM-Based DA, a new architecture named Adder-Based DA replacing ROMs with serial adders is proposed in this thesis. This new architecture cost much less area than traditionally ROM-Based DA since the ROMs are all replaced by small serial adders. An IDCT chip with 16 mm^2 core area by CCL CMOS standard cells is designed and implemented in this thesis and speed of 98 M pels/ sec is achieved in simulation of VERILOG.