分裂閘極式快閃記憶晶胞的可靠性研究

Abstract

本論文評估的非揮發性記憶晶胞僅需單壹五伏特電源即可作資料編寫或抹 除,並且沒有抹除過度的問題.不同的複晶矽閘極厚度和兩層複晶矽間的介 電層厚度將被用來作為實驗樣本參數. 實驗樣本的非揮發性元件特性 ,如 編寫,抹除,讀取干擾耐性和資料重複編寫/抹除能力是評估重點. 實驗結 果證明漂浮複晶矽閘極的周圍邊緣尖銳程度是影響分裂閘極式快閃記憶晶 胞抹除能力的最重要因素. 在傳統作為漂浮閘極的複晶矽沉積後在複晶矽 上面進行局部氧化製程並作非等向電漿蝕刻, 將會形成所需具有銳利邊緣 的漂浮閘極. 較薄的介電層和更尖銳邊緣的複晶矽閘極可以改善抹除能力 但也可能使元件的可靠性劣化, 尤其是讀取干擾耐性. 本研究所探討的分 裂閘極式記憶晶胞在讀取資料時, 電子從漂浮閘極穿邃兩層複晶矽間的介 電層到控制閘極,可能是造成讀取干擾的原因.經非揮發性元件特性評估顯 示1700埃厚度的漂浮閘極配合局部氧化1800埃的樣本是最適化製程組合 .由於採用雙閘極結構可以得到較佳熱電子注入效率,當源極施以12伏特偏 壓,只要20微秒即可完成資料編寫. 由於漂浮複晶矽的尖端放電效應,當控 制極施以14伏特偏壓,在100微秒內即可完成資料抹除. 記憶晶胞經最適化 製程製造,可達到一百萬次重覆編寫/抹除能力並可連續十年讀取資料也不 會造成資料流失. In this thesis, a split gate Flash memory cell which requir- es only single 5v power supply for both programming and erase, and was an over-erase-free Flash cell had been interpreted and evaluated. Different process recipes for the thickness of float- ing poly-Si gate and interpoly dielectric were utilized for sam- ples preparation. We also evaluated some nonvolatile memory dev- ice characteristics such as program, erase, read disturb and en- durance. The sharpness of edge of floating poly- Si gate was the most important factor for erase characteristics. In addition to the conventional formation of floating gate by polisilicon depo- sition process, LOCOS oxidation on the polisilicon film was added before RIE etch process. Thinner dielectric and sharper edge of floating gate would be preferred. However, it degraded the device reliability especially in read disturb, which is pre- sumably due to the electron tunneling from floating gate to the control gate during read operation. The recipe using 170nm floa- ting poly-Si gate following with 180nm LOCOS oxidation on poly-Si was proved to be the optimized recipe by read disturb evaluation. The one million cycles endurance is achievable and could be read fopr 10 years without data loss problem.