完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 周宗平 | en_US |
dc.contributor.author | Tzung-Ping Chou | en_US |
dc.contributor.author | 李崇仁 | en_US |
dc.contributor.author | Chung-Len Lee | en_US |
dc.date.accessioned | 2014-12-12T02:13:50Z | - |
dc.date.available | 2014-12-12T02:13:50Z | - |
dc.date.issued | 1994 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT830430115 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/59309 | - |
dc.description.abstract | 在本論文中, 我們提出利用軟體指令運算 Software Emulation來加速障 礙模擬器的技術。軟體指令運算是指一個以閘級電路表示方式的模組可被 軟體指令來取代, 因此障礙效應可藉由符號運算的方法來傳遞。利用這種 方法, 障礙效應可以快速通過一個複雜的模組因此省下大量的閘級計算時 間。此外, 我們也修改一些傳統的障礙模擬技巧以適應高階電路並加速此 障礙模擬器。使用這些技巧, 我們可同時得到階層式電路快速的好處並保 有和閘級電路相同的精確度在。且這方法的記憶體的使用量也很小。 In this thesis, a new fault simulation technique is presented. The technique uses software emulation to speed up the fault simulator. The keyword "Software Emulation" means that a module, which should be a netlist which describes connections for each gate at the gate level representation, is replaced by a set of software instructions. Hence fault effects can be propagated by symbolic operation. In this way, the fault effects can pass through a complex module quickly and a large amount of gate level evaluations is saved. Some traditional fault simulation techniques are modified in this work to fit the high level circuits and to speed up this fault simulator. In this way , We can take the advantage of high simulation speed of hierarchical level circuit and reverse the accuracy of the gate level circuit simulation at the same time. And the memory usage is also small in this method. | zh_TW |
dc.language.iso | en_US | en_US |
dc.subject | 軟體指令運算; 障礙模擬; 模組; 符號運算 | zh_TW |
dc.subject | Software Emulation; Fault Simulation; Module; Symbolic Operation | en_US |
dc.title | 使用軟體指令運算的障礙模擬器 | zh_TW |
dc.title | A Fault Simulator Based on Software Emulation | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 電子研究所 | zh_TW |
顯示於類別: | 畢業論文 |