IS-54數位行動通訊系統之時序回復電路設計

Abstract

時序回復技術在數位通訊系統中扮演著一個極為重要的角色，因為接收器 在進行信號處理時需要正確的時序。在行動通訊系統中，接收訊號不僅會 受到加成性高斯白雜訊的干擾，也會受到多重路徑衰落效應的影響。此時 要從衰減後之訊號重建出正確的時序變得較困難。在本論文中，我們針對 一種利用時序誤差檢測器、數位迴路濾波器以及數控式振盪器組成的非線 性數位時序回復技術進行評估。我們將此數位時序回復架構應用在北美 IS-54 數位行動通訊系統上。在此系統中，由於只有前14個字符為同步序 列，因此我們需要有個收斂快速並且穩定的數位時序回復電路架構。根據 電腦模擬的結果顯示，此數位時序回復電路架構具有不錯的性能表現，並 且在硬體設計上複雜度不高。根據 Verilog 模擬的結果，我們完成了此 一數位時序回復電路的硬體實現，並且驗證其功能正確無誤。 Timing recovery technique plays a very important role in the digital communication system, because correct timing is necessary for signal processing in the digital receiver. In mobile communications, the received signal is not only interfered by the additive white Gaussian noise (AWGN), but also affected by the multipath fading effect. In this situation, regenerating the timing information from the faded signal is difficult. In this thesis, we evaluate a class of the nonlinear digital timing recovery techniques using Gardner's timing error detector, digital loop filter and digital controlled oscillator (DCO). In IS-54 system, a fast converging and stable timing recovery scheme is required because the synchronization sequence is only 14 symbols long. From computer simulations, we find that the digital timing recovery scheme has good performance, low computation and low hardware complexity. A VLSI implementation of the digital timing recovery scheme is completed and has been verified successfully in Verilog simulations.