MPEG-2視訊解碼器之VLD-RLD模組電路設計

Abstract

本篇論文中我們提出了一個 MPEG-2 解碼器的 VLD-RLD 模組 .此 VLD- RLD模組的功能是作資料的分送,將 slice 階層以上的固定長度資料分送 給系統控制單元 , 並解析可變動長度碼 , 輸出離散餘弦轉換系數給反量 化/反向離散餘弦轉換模組(IQ/IDCT module) . 為了符合一個時鐘週期輸 出一個離散餘弦轉換系數的要求 , 我們採用平行架構 .並且運用管線式 解碼的技巧來縮小離散餘弦轉換系數編碼表 . 為進一步減少面積, 在 VLD 與 RLD 之間及 RLD 與 IQ/IDCT 之間都設計成不需緩衝器 .我們運 用了傳統直接畫電路圖的工具及高階設計的技巧來實現我們的設計. 並 在 27Mhz 的系統時鐘及聯華 0.8 微米閘陣列單元庫的條件之下 , 以 Verilog 硬體描述語言及多種不同格式的影像資料驗證其功能之正確性. The function of the VLD-RLD module presented in this thesis is to parse the video bistream, forward the fixed length part above slice header to System Controller, demap the variable length codeword into a decoded symbol and output the dct- coefficients to the IQ/IDCT module of the MPEG-2 decoder. We adopt a parallel structure to fulfill the need of outputing one dct-coefficient one clock cycle regardless of their original coding format. The pipeline decoding scheme is also used to reduce the size of dct-coefficient codebook. No buffers exist between VLD and RLD, as well as RLD and IQ/IDCT to further reduce the area. We use both traditional schematic entry tool and high level design technique to realize our circuit design. Based on UMC 0.8mu gate array library and a system clock of 27 Mhz, the gate level netlist have been verified by the Verilog- XL simulation with various bitstreams of different picture formats.