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dc.contributor.authorWu, Woei-Cherngen_US
dc.contributor.authorChao, Tien-Shengen_US
dc.contributor.authorChiu, Te-Hsinen_US
dc.contributor.authorWang, Jer-Chyien_US
dc.contributor.authorLai, Chao-Sungen_US
dc.contributor.authorMa, Ming-Wenen_US
dc.contributor.authorLo, Wen-Chengen_US
dc.contributor.authorHo, Yi-Hsunen_US
dc.date.accessioned2014-12-08T15:07:34Z-
dc.date.available2014-12-08T15:07:34Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0636-4en_US
dc.identifier.urihttp://hdl.handle.net/11536/5968-
dc.description.abstractHigh-performance CESL strained nMOSFET with HfO(2) gate dielectrics has been successfully demonstrated in this work. It is found that, the transconductance (g(m)) and driving current (I(on)) of the nMOSFETs increase 70% and 90%, respectively, of the increase of devices with a 300 nm capping nitride layer. A superior HfO(2)/Si interface for CESL-devices is observed, demonstrated by an obvious interface state density reduction (6.56x10(11) to 9.85x10(10) cm(-2)). Further, a roughly 50% and 60% increase of g(m) and I(on), respectively, can be achieved for the 300 nm SiN-capped HfO(2) nMOSFET without considering charge trapping under pulsed-IV measurement.en_US
dc.language.isoen_USen_US
dc.titlePerformance enhancement for strained HfO(2) nMOSFET with contact etch stop layer (CESL) under pulsed-IV measurementen_US
dc.typeArticleen_US
dc.identifier.journalEDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGSen_US
dc.citation.spage161en_US
dc.citation.epage164en_US
dc.contributor.department電子物理學系zh_TW
dc.contributor.departmentDepartment of Electrophysicsen_US
dc.identifier.wosnumberWOS:000254170700042-
Appears in Collections:Conferences Paper