完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Wu, Woei-Cherng | en_US |
dc.contributor.author | Chao, Tien-Sheng | en_US |
dc.contributor.author | Chiu, Te-Hsin | en_US |
dc.contributor.author | Wang, Jer-Chyi | en_US |
dc.contributor.author | Lai, Chao-Sung | en_US |
dc.contributor.author | Ma, Ming-Wen | en_US |
dc.contributor.author | Lo, Wen-Cheng | en_US |
dc.contributor.author | Ho, Yi-Hsun | en_US |
dc.date.accessioned | 2014-12-08T15:07:34Z | - |
dc.date.available | 2014-12-08T15:07:34Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-0636-4 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/5968 | - |
dc.description.abstract | High-performance CESL strained nMOSFET with HfO(2) gate dielectrics has been successfully demonstrated in this work. It is found that, the transconductance (g(m)) and driving current (I(on)) of the nMOSFETs increase 70% and 90%, respectively, of the increase of devices with a 300 nm capping nitride layer. A superior HfO(2)/Si interface for CESL-devices is observed, demonstrated by an obvious interface state density reduction (6.56x10(11) to 9.85x10(10) cm(-2)). Further, a roughly 50% and 60% increase of g(m) and I(on), respectively, can be achieved for the 300 nm SiN-capped HfO(2) nMOSFET without considering charge trapping under pulsed-IV measurement. | en_US |
dc.language.iso | en_US | en_US |
dc.title | Performance enhancement for strained HfO(2) nMOSFET with contact etch stop layer (CESL) under pulsed-IV measurement | en_US |
dc.type | Article | en_US |
dc.identifier.journal | EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS | en_US |
dc.citation.spage | 161 | en_US |
dc.citation.epage | 164 | en_US |
dc.contributor.department | 電子物理學系 | zh_TW |
dc.contributor.department | Department of Electrophysics | en_US |
dc.identifier.wosnumber | WOS:000254170700042 | - |
顯示於類別: | 會議論文 |