運用基因法則構建半導體測試區現場排程模式

Abstract

近年來，由於晶圓製造廠的蓬勃發展，也促成測試、切割與封裝產業的成 長與擴張，競爭也日趨白熱化。半導體測試區之測試產品係承接為前段晶 圓製造廠之晶圓成品以及外包的切割與封裝廠之已封裝晶粒兩種。前段與 外包廠商不穩定的輸出，使得測試批量呈現動態性的到達，而現場機台設 置之變換亦是系統變異的來源。所以，如何能在達成顧客交期的情況下， 使得設置次數與時間最小，為半導體測試區排程規劃之重點。本文擬在達 成顧客交期與減少機台設置的目標前提下，運用基因法則之理念發展一適 合半導體測試區之現場排程模式。本文之現場排程模式在承接湯[18]之主 生產排程後，分成投料批量選取規劃及工兩個階段。在投料批量選取規劃 階段，以產能分配的方式選現場投料與派取適當的測試 批量型號與數量 ，而後在現場投料與派工階段，利用基因法則隨機搜尋的特性，選擇測試 批量之最適投料機台與最佳派工序列。在近似最佳化的考量下，落實投料 批量選取規劃的規劃結果。由最後的驗證結果看出，本文所發展之現場排 程模式確實能在達成顧客交期下，減少測試機台的設置次數與時間，符合 半導體測試區之排程目標。 Recently, because of properous development of wafer fabrication, the growing and expansion of testing, cutting and packaging industries are promoted and thecompetetion also become more and more white-hot day after day. The source of testing product in semiconductor testing factories includes the wafer of the front- end and die of the subcontructed cutting and packaging factories. The unstable output of the front-end and subcontractors makes the dynamic arrival of testing lots; and the setup change of machines is also the source of systematic variances. The thesis uses the idea of genetic algorithm(GA) to develop a sho p floor scheduling model fitted to semiconductor testing factories under the meeting of the customers' due-date and the decreasing setup times of the machin es. The shop floor scheduling model uses the MPS planned by Tang[18]. It is di vided into two stage : (1) lots selection, (2) releasing and dispatching. In lots selection stage, it chooses appropriate testing lots and quantity with the considerations of order's due- date and capacity limitation. Then, in releasi ng and dispatching stage, it chooses the appropriate machine and dispatching s equence by using the characteristics of GA'sr andom search. Through the search,optimum. Hence the planning goal of lots selection can be achieved.the planni ng result will converge to an approximate. The simulation results show that the shop floor scheduling model can decrease the setup time and frequency under the meeting of customers' due-dates. It thus fits the scheduling goals of the semiconductor testing factories.