低功率二階邏輯最佳化

Abstract

功率的消耗在超大型積體電路上日趨重要。有許多研究投入如何設計 低功率電路，在邏輯化簡時如何降低功率也是很重要。 在這論文中，我們針對二階邏輯電路提出一個降低功率的方法，因為功率 消耗和輸入信號的高態機率和轉換機率有關，所以一個小面積的布林邏輯 可能會比大面積時消耗更多的功率。我們在 ESPRESSO 演算法中加入一些 方法降低功率的經驗方法，這些方法使用高態機率和轉換機率兩個參數， 以這兩個參數來決定那一個變數相乘項先化簡、如何選擇化簡的方向、判 斷化簡是否有省功率、變數相乘項的選擇等等。如使用靜態 PLA或動態 PLA來設計, 各可省 11.68 % 和 1.44% 的功率；如使用一般邏輯匣, 和 Simplify 比, 則省 8.27%。 Recently, power consumption becomes an important issue in VLSI circuit designs. Many proposed researches make a contribution to the topics of low power design. Reduce power consumption of circuits during logic minimization is also significant. In this thesis we present a Boolean technique for reducing the power consumption in two- level combinational circuits. Because power consumption of a circuit depends on the signal probabilities and transition densities of primary inputs, the network with smaller area may have larger power consumption than that of the one with larger area. We modify ESPRESSO algorithm by adding our heuristics that bias the logic minimization toward lowering the power dissipation. In our heuristics, signal probabilities and transition densities are two important parameters. If we use static PLA or dynamic PLA to implement circuits, the results of our method show an average of 11.68 % and 1.44% improvement inpower consumption compared to ESPRESSO package, respectively. We also study the power consumption in two-level combinational circuits using general logic gates to implement. The corresponding reduction of power consumption compared to Simplify package is 8.27%.