以混合電壓源與混合邏輯型態為主的管線化乘法器設計

Abstract

在這篇論文中提出一個低功率管線化的乘法器的設計。乘法一般都可 被看做為是加法與平移的動作的結合，因此我們提出一個新的加法器的設 計。這加法器結合了降低電壓源與不同的邏輯型態的優點。此外，在我們 所提出的管線化乘法器架構中使用混合電壓源的架構可以降低功率消耗達 百分之二十五左右。在這種架構裡，較高的電壓源被用來加速決定性延遲 的電路部份而較低的電壓源則是在滿足時序要求下被用來減低功率消耗。 的電壓源則是在滿足時序要求下被用來減低功率消耗。 基於混合電壓源的架構我們也提出了低功率管線化的乘法器的設計。經由 HSPICE的模擬，加法器有較低的功率與速度度的比值而乘法器有較低的功 率消耗。 In this thesis, we proposed a low power pipelined multiplier design. Multiplication can be viewed as the combinations of shift and addition. Hence, we proposed a new 1-bit full adder circuit design. It combines the advantages of reducing supply voltage and using different logic styles. In addition, we use mixed supply voltages to reduce the power consumption by another 25% in our proposed architecture. In this architecture, higher supply voltages could speed up the critical delay block and lower supply vtage could decrease the power consumption while meeting the timing constraints. Based on the idea of mixed supply voltages, the low power pipelined multiplier is proposed in this thesis. By Hspice simulation, the proposed full addercircuit has the lowest power/ speed ratio and the pipelined multiplier has achieve significant power reduction.