具同時性之視訊處理器之設計與實作

Abstract

視訊處理器非常適用於各種不同的影像標準﹐具有高度的系統發展的彈性 。為了達到高產出及高硬體效率的目的﹐我們提出了一個具同時性視訊處 理器架構。它包含了三個具有平行性的向量運算單元-算術單元、乘法單 元以及離散餘弦轉換/反離散餘弦轉換單元。這三個單元使用向量管線的 架構來增加效率以及減少時脈週期。有六個晶片內記憶體區塊來提供足夠 的資料頻寬﹐並減少所需的輸入/輸出次數。另有一個純量處理單元負責 設定參數以及程式流程的控制。為了完全利用上述平行運算單元﹐我們設 計了一個同時性的控制單元來負責指令排程以及消除危障。這個控制單元 採用了保留表、重新命名、亂序執行及依序結束的技術。經由 Verilog- XL 的驗證﹐我們設計的視訊處理器可以達到 CIF 的格式H.261 即時影像 壓縮的標準。我們用現場可程式化邏輯陣列元件— Xilinx XC4010 來作 原型實作及驗証﹐並且用邏輯分析儀來測試其正確性。 The video signal processor (VSP) is very suitable for various video standards and provides high flexibility for system development. In order to offer highthroughput and hardware efficiency, we propose a concurrent VSP architecture. Our VSP contains three vector function units that work in parallel. The threevector function units include the arithmetic unit, the multiplier unit andDCT/IDCT unit which adopt vector-pipeline architecture to increase thethroughput and reduce the clock cycle time. There are six on-chip memorymodules to support the data bandwidth for the vector function units and reducethe I/O traffic. A scalar processing unit is employed to process the scalarinstructions that set parameters and control program flow. To take the fulladvantages of the parallel function units, we design a concurrent control unitwhich eliminates hazards and schedules instructions. The control unit uses thetechniques of reservation stations, renaming buffer, out-of-order executionand in-order completion. With these design considerations, our VSP can encodereal time full-CIF H.261 video in the Verilog simulation. Because of thecomplexity of our VSP, we also verify the design on Xilinx XC4010 FPGA devices.The test results from the logic analyzer show the function correctness.