粗糙複晶矽所製新奇堆疊式電容器於高密度動態隨機存取記憶體之應用

Abstract

在本論文中,提出一項利用粗糙複晶矽製成微小電容器的技術.此技 術是先選擇一適當的絕緣基底,並在其上沉積複晶矽層,然後我們採用離子 佈植摻雜高濃度的磷至複晶矽層.在隨後的處理,我們也發現利用此方式比 利用POCl3擴散摻雜的方式能增加更多的凹痕結構,而這些凹痕結構影響著 表面積增加的程度.離子佈植後須在高於800 C的溫度下進行退火,使得經 離子佈植形成的非晶矽層經由退火程序再轉回複晶矽層,同時磷原子偏析 到晶界.發現經由磷摻雜的複晶矽在晶界有良好的蝕刻效果,並在表面形成 許多微小的凹痕結構.我們利用掃描式電子顯微鏡觀察表面的形態.根據穿 透式電子顯微鏡分析的結果,發現磷酸對晶界會作選擇性蝕刻.因為晶界有 較多的晶體缺陷及低能量晶格,使得摻雜的磷原子容易積聚在晶界,而造成 明顯的蝕刻效果.如果這些微小的凹痕結構再經過雙氧水,氨水,和水的混 合液處理後會轉變成微小的島狀結構.這些微小的島狀結構更有助於表面 積的增加.我們也能從掃描式電子顯微鏡清楚地觀察此微小的島狀結構. 利用以上方法所形成的粗糙複晶矽當做電極,並在其上沉積介電層製成電 容.觀察其表面積效應對電容值的影響,發現這些有微小島狀結構的複晶矽 電極能有效地增加電容值至3.6~4倍.此新奇電容器比其它結構的電容器容 易製造且有較少的製成步驟,因此非常具有應用於64Mb或更高密度的動態 隨機存取記憶體之潛力. In the thesis, a new method to produce a microminiaturized capacitor with a roughened surface electrod is achieved. The method involves depositing a firstpolycrystalline layer over a suitable insulating substrate. The polysilicon layer is heavily doped with phosphorus by ion implantation followed by heating. In the following treatment, we find that more micro cavities can be formed by ion implantation than by POCl3 diffusion. Moreover, these micro cavities influence the degree of surface roughness. After ion implantation, the structure is annealed at above 800 C to crystallize the amorphous silicon into polycrystalline phase and segregate the phosphorous atoms to the grain boundaries. By immersing into the H3PO4 solution, some micro cavities will be formed on the surface of polysilicon. From the SEM photographs, these micro cavities can be clearly observed. To explore the etching mechanism, according to the TEM photographs, high etching rate at the grain boundaries in the H3PO4 solution can be concluded to be the main reason of the formation of these cavities for the phosphorus-doped polysilicon films. Thereafter, the micro cavities will be changed into the micro islands through the NH4OH-H2O2-H2O treatment. The micro islands facilitate the surface area enlargemnent. The micro islands can be also obviously observed from the SEM photographs. The roughened poly-Si can be used as the bottom electrode of the novel capacitor. The surface of stacked electrodes covered with micro islands willenlarge the surface area effectives and increase the capacitance of the novelcapacitors. Improvement of 3.6~4 times storage capacitance can be obtained with such a roughened poly-Si electrode. This capacitor is easier to fabricateand fewer process steps are needs as compared with other proposed structures.The novel capacitor is thus promising for 64 Mb and higher-density DRAMs.