快閃記憶元件的設計方法

Abstract

本論文中, 我們提出了一個設計高速度且高可靠性快閃記憶體( flash EEPROM )的方法. 一個經由修正一維基板射入( substrate injection )模型而可以適用於二維數值分析之閘極射入( gate injection )機率模型將在此論文中作一介紹. 此模型乃利用通道熱載子 造成之能障降低效應來表示二維的射入機率. 我們便利用此一有效的模型 來模擬不同汲極結構元件之寫入速度以及氧化層陷阱捕捉電荷速度. 模擬 結果顯示欲得一高速度且高可靠性的快閃記憶元件, 在寫入時射入的熱載 子必須要寬廣的分布, 而一 P 雜質層包圍之非對稱淺摻雜汲極結構( p- pocket-surrounded asymmetric LDD structure )乃於文中證明可滿足此 一要求. A design methodology for high-speed and high-reliable flash EEPROM is presented in this thesis. By modifying a 1-D substrate injection model, agate injection probability model for 2-D numerical analysis is introduced,in which a channel hot-electron enhanced barrier lowering term is used to represent the 2-D injection probability. With this model, the writing speedand the generation of oxide-trapped-charges for various drain structures aresimulated. The simulation results have shown that in order to obtain a high-speed and high-reliable EEPROM cell, the distributin of hot-carriers under writing condition must be widened and a p-pocket-surrounded asymmetric LDDstructure has been shown to satisfy the requirement.