標題: | 具未知值之高階障礙模擬 High Level Fault Simulation with the Unknown Value |
作者: | 吳明學 Wu, Ming-Shae 李崇仁 Lee Chung-Len 電子研究所 |
關鍵字: | 未知值;Unknown Value |
公開日期: | 1995 |
摘要: | 在本文中,我們提出在高階處理未知值之障礙。所謂未知值是指於序 向電路模擬中在資料的二進位表示式上有些位元的值是未知的。我們發展 一些演算法,利用基本的布林、位移和加法運算來模擬具有未知輸入的函 數模組,如加法器、乘法器、位移器和多工器。在我們的演算法中,我們 只需四個CPU指令就可模擬任何長度的加法器,此相對於在1位元閘級 階層的全加器中則需18個CPU指令來模擬。使用這些演算法,可以將 障礙效應快速地通過無障礙模組而無需模擬大量。從實驗的結果中,我們 提出的方法比在閘級作模擬運算的方法,有需時較短及達到較高的精確性 的優點。 In this thesis, a new fault simulation technique for handling the unknown value in high level is presented. The keyword "Unknown Value" means that values of some bits of the bus are unknown. We develop the algorithms using Boolean and ADD operations to simulate the functional modules, such as adder, multiplier, shifter and multiplexer, which have unknown input values. Only 4 CPU instructions are required to simulate an adder regardless its size, but it needs 18 CPU instructions for 1-bit full adder on gate level. In this way, the fault effects can pass through the good modules quickly without large amout of gate simulations. From the experimental results, the proposed methods can take shorter time and achieve higher accuracy as compared to those simulation methods on gate level. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT840430098 http://hdl.handle.net/11536/60705 |
Appears in Collections: | Thesis |