利用延遲變異分析之冗餘功率計算

Abstract

在本篇論文中，我們提出一種系統性的方法來估算延遲平衡電路中之部分 冗餘（partialglitch）功率。部分冗餘功率主要是由於輸入信號到達閘 輸入端之時間差異所造成，而此 差異在延遲平衡電路中是來自於信號到 達時間之變異。因此我們發展一種分析方法來估算信號到達時間之變異並 發現每一閘之變異數包含兩部分：局部產生之變異及前級傳播之變異。我 們再利用蒙地卡羅模擬分析，則可估算閘之部分冗餘功率。我們並介紹數 種平衡非勻相電路中不平衡路徑的方法。我們並以一簡單之勻相電路及兩 個已平衡之16位元乘法器為例子以示範我們的功率估算法。 In this thesis, we propose a systematic method to estimate the partial glitch power in a delay balanced circuit. Partial glitches come from the skew of input arrival time and this skew may result from the arrival time variance. Hence we developed an analysis method to estimate the arrival time variance which was found to consist of two parts: locally generated variance and the variance which propagates from previous stage. We use Monte Carlo simulation to estimate the statistical partial glitch power of a gate coresponding the arrival time variance. We also introduce some methods to balance the heterogeneous circuit. We use a simple homogeneous circuit and two delay balanced 16 by 16 multipliers as examples to demonstrate our power estimation method.