Accurate logic-level power simulation using glitch filtering and estimation

Abstract

Power estimation tool is needed to be more fast and accurate when the power consumption is the chief concern during the chip design. Logic-level simulator is a good choice to estimate the power consumption of a chip design. In this paper we attempt to improve the accuracy of a logic-level simulator using glitch filtering and estimation techniques. We use logic-level simulator to filter some glitches and estimate the glitch power. We use slope of transition and time interval of two consecutive transitions to decide whether these transitions is partial glitches or full transitions. We estimate the transition power of each transition event and summed them up. The power simulation error is reduced from 35.8% to 7.9% referring to the Spice simulation.