積體電路晶圓缺陷管制圖之經濟性設計

Abstract

計數值管制圖中的缺點數管制圖是積體電路生產線上最常用的品質管制方 法, 其目的在監控缺陷數, 使晶圓的生產有高而穩定的良率, 但隨著積體 電路晶圓面積不斷增大, 晶圓表面缺陷的分佈出現群聚現象, 使得以波瓦 松分配為依據的缺點數管制圖不再適用. 新近的研究中, 針對晶圓缺陷群 聚現象的處理方法有二, 分別為: (1)使用尼曼A型分配取代波瓦松分 配,(2)使用群聚現象分析加以處理, 然後構建出修正缺點數管制圖. 本研 究將利用兩個主要處理晶圓缺陷群聚現象的方法與Duncan所提經濟管制圖 的觀念, 進行管制圖之經濟性設計, 構建出管制圖的經濟模式, 並以實際 IC生產線上的數據為例, 求出管制圖之最佳的抽樣頻率, 樣本大小與管制 界限, 以決定一成本最低的管制圖. 本研究並針對模式中之參數進行敏感 性分析, 以提高分析結果的正確性. The control charts are the most useful tool of statistical process control(SPC). Among various types of control charts, c- chart is used in IC fabrication to monitor the defect counts on wafers. As the surface area of wafer of IC increases, the clustering phenomenon of the defects becomes more apparent. Consequently, the clustered defects frequently cause many false alarms when the conventional c-chart based on Poisson-based c- chart is used. To reduce the number of false alarms caused by clustered defects, Albin and Friedman suggested to construct the defect control charts based on the Neyman type-A distribution. One of the multivariate statistical techniques, cluster analysis, can also be utilized to modify the conventional c- chart. The purpose of this thesis is to design an economic control chart by using the Duncan's economical idea. Economic models for defect control charts based upon Neyman type-A distribution and cluster analysis are derived. The models can assist the engineer or analyst to select a sample size, a sampling frequency, and the control limits with minimum cost. A numerical example is given to demonstrate the effectiveness of the derived economic models. Sensitivity analysis of the models are also discussed.