氮化複晶矽表面所製複晶矽間介電層在高密度快閃記憶體元件之應用

Abstract

快閃記憶體(Flash Memory)擁有著許多優於一般其他非揮發性記憶 體(Nonvolatile Memory)元件的特性，使其在IC卡、通訊市場、消費性 電子產品上廣受採用。隨著提高 元件密度、縮小元件尺寸下，降低複晶 矽間介電層(interpoly dielectric)的厚度，將能有的使元件在垂直方向 上做尺寸縮小且提高閘極耦合係數值(Gate Coupling Ratio) 然而想 在粗糙的複晶矽表面上成長品質良好且薄的薄膜介電層，如氧化矽/氧化 氮/氧化矽(Oxide/Nitride/Oxide, ONO)，或氮化矽/氧化矽(Nitride/ Oxide, NO)必更加困難。此實驗在且不增加製程困難度下，採用各種氮化 複晶矽表面的方法來改善複晶矽間介電層的特性。首先針對成長氧化氮/ 氧化矽介電層，在成長氧化矽的低壓爐管中先通入氨氣(NH3)一段時間來 氮化複晶矽表面，之後再通入氫 化矽（SiH2Cl2）氣體成長氮化矽薄膜 。因為氮為五價原子將會偏析到複晶矽的晶界上且夠形成氮矽表面鍵結( Si-N bonds)。如此一來後續成長氧化矽時將能有效阻止氧原子在複晶矽 之晶界快速的成長而得到較平滑的複晶矽與介電層界面，進而降低漏電流 。 至於成氧化矽/氧化氮/氧化矽介電層 ， 由於必須先通入 稀釋過的氧氣在複晶矽表面成長氧化矽薄膜，而氧原子會在晶界加速氧 化。因此在成長氧化矽之前，先在複晶矽表面在但氣電漿處理（N2- Plasma）。因其基板 未加偏壓，氮氣受激發後產生的氮原子將利用擴散 作用到複晶矽表面，之後在850 oC成長 氧化矽時，預先熱驅入(thermal driven-in）處理，使氮原子在晶界作良好的鍵結（Si-N bonds），防止 氧原子在晶界快速成長，而得到一個較平滑的複晶矽氧化矽介面，能有效 的降低高電場時的漏電及崩潰電場。 The flash-type EEPROM or flash-type EPROM is expected to be a most promising device for the next-generation nonvolatile memory market due to the growing demad high density non-volatile memory for portable computer and telecommunicatin marencourages serious interest in flash memory. The decrease of thickness ofinterpdielectric will be effective to scale vertically the device geometries and meanwhigh gate capacitance-coupling ratio( CRE) for high density Flash memory devices.However, it is very difficult to grow a thin and high quality interpoly dielectric on the rough floating polysilicon gate, such as Nitride/Oxide (NO),orOxide/Nitride/Oxide (ONO). For NO structure, the concerned issues are higher leakage in the low field resulting in worse immunity to charge retention, and higher threshold voltage shift. In my experiment, we adopt two steps method of growing dielectric to obtain ONO like structure which can resolve the first problem, furthermore we adopt the process by using poly-Si with NH3 passivation in the LPCVD prior to nitride depositionwhich can significantly resolve the second issue. For ONO structure, the concerned issues are high leakage current in the high field, lower breakdown and shorter dielectric lifetime, attributed to the asperity of bottom interface. In my experiment, we adopt N2 plasma to form Si-N bonds in the groove or grain boundary of poly-Si and following thermal driven-into gain good bonding which can retard the oxidant to accelerate grown at grain boundary, thus a smoother bottom interface obtained. As a result, the concerned issues enable to be resolved.