標題: 超純量複雜指令集微處理機執行核心之探討
Issues of the RISC Execution Core for a Superscalar CISC Microprocessor
作者: 許裕仁
Sheu, Yuh-Ren
陳昌居
Chang-Jiu Chen
資訊科學與工程研究所
關鍵字: 超純量微處理機;ROP86;superscalar;register renaming
公開日期: 1996
摘要: 我們觀察發現,提高微處理機性能的方法,除了一昧的拉高微處理機執行 時脈外,對微處理機內部架構的改變,亦能對微處理機整體性能有相當顯 著的加強。這點在Intel x86架構微處理機的發展過程中尤為明顯。 在80486中引為管線的作法;在Pentium裡加入了超純量的設計,以期能在 同一週期執行兩道不同的x86指令,更進一步提升微處理機效能。但由於 x86指令集本身的限制,像Pentium這種採用兩道管線在x86指令層次的超 純量設計,並不能總是達到預期的目標 -- 在同一週期執行兩道不同的 x86指令。為了克服這個問題,我們提出一個CISC/RISC混和型的設計 - 具有CISC的前端解碼單元和RISC的後端執行單元。 利用前端解碼單元將 一個x86指令根據其語意分解為多個簡單的微指令,再將這接分解出來的 微指令交由後端的RISC執行單元來計算。這種設計可有效的利用不同x86 指令間的平行度來提高效能。此外,我們亦可利用現成的RISC技術甚至既 存的設計來完成後端的執行單元,這種作法可大法節省開發於除錯的費用 。在這篇論文中,我們將討論將既存的RISC設計應用在這個執行核心時所 需面對的問題,並提出適當的修正方法,以便能有效的運用。此外,我們 亦評估採用這種CISC/RISC混和型設計對原有純量設計以及在x86指令層次 的超純量設計作一比較。 Originally, Intel x86 processor is a scalar CISC processor, i.e. it can finish one x86 instruction per cycle at the most. Due to the inhibitive cost and the limitation of semiconductor process technology and electrical property, we cannot lift up the clock speed of x86 processor unendingly to gain much more performance improvement. It seems straightforward that we can build a 2-way issue superscalar x86 processor just by adding another one integer pipeline to he original scalar x86 architecture. But the inherent characteristics of x86 instruction set constrain the overall improvement.One way to approach the superscalar x86 processor design is to start with a pure microcoded scalar implementation, without hardwired control and special techniques employed in the Intel x86 processor. The goal in this case would be to archive parallel execution of microinstructions in a superscalar pipeline. The advantages of this approach is that it converts complex x86 instructions into sequences of microinstructions that are much easier to deal with.Although we can design a superscalar CISC processor with RISC execution core to improve overall performance. In this design, the other advantage is that we can save a lot of money and time by using existed technique or implementation for RISC processor to build the RISC execution core [7]. But the thing is not so good, we need to adapt the existed RISC design to fit the CISC architecture. We will address theses issues and advise possible solutions.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT850392018
http://hdl.handle.net/11536/61765
Appears in Collections:Thesis