數位電路之延遲測試與障礙模擬

Abstract

本論文分成兩部分，前半部研究高可靠性的延遲障礙測試，後半部則 著重在障礙模擬應用在分散式平行處理的架構上。關於延遲障礙測試部分 ，首先提出一種新測試方法-振盪環測試，並針對此測試方法提出其測試 架構。此法產生之測試型樣，可測到所有的定值障礙、所有的閘延遲障礙 與部分的路徑延遲障礙。本方法尋找可敏化路徑的部分集合，在每條路徑 加上反相或正相迴授，形成一個反轉階級為奇數之環。當輸入的測試型樣 能夠敏化該路徑時，此環便會振盪。本方法採用多重振盪環策略，以減短 測試型樣的長度。繼之，提出一套判定嚴謹式非可測路徑延遲障礙的理論 分析，將路徑的分合形式歸納成七種，並推導每一種分合形式的嚴謹測試 條件，據以提出路徑延遲障礙的非可測判定方法。結果顯示標準電路中， 非可測路徑延遲障礙所佔的比例非常高。最後，提出一個函數電路的路徑 延遲障礙的測試型樣產生器。先將無法在一個型樣同時測試的障礙分到不 同的障礙集合，以減少同時測試的候選障礙之選擇失敗機率。此型樣產生 器是以向量並行處理模式寫成，可有效地減少運算時間與記憶體。實驗結 果顯示本方法非常快速，而且產生之測試型樣具有很高的測試效率。 關於障礙模擬部分，首先提出一套兩進式障礙模擬方法，可測到並除去傳 統障礙模擬誤判為非可測之障礙。因為此類障礙非常耗費障礙模擬時間， 除去這些障礙後，障礙模擬的速度平均提高二至三倍。繼之，研究工作站 網路連接之分散式系統環境，將兩進式障礙模擬應用到型樣切割模式的分 散式平行障礙模擬。因為每台機器只模擬一部分的測試型樣，並可利用網 路的訊息傳遞，刪除任何一台機器測到的障礙，達到超線性的加速性能。 This dissertation is divided into two parts. The former investigates delay fault testing and the latter is dedicated to distributed fault simulation.Concerning delay fault testing, a new test methodology, oscillation ringtest, and its associated testing circuit organization for digital circuitsare first proposed. The generated test vectors can detect all the stuck- atfaults, all the gate delay faults and part of path delay faults. This method tries to find a set of sensitizable paths to cover all the circuit lines. Aninverting feedback or noninverting feedback is added to the path to form aring with odd inversion parity. A test vector which sensitizes the pathmakes this ring oscillate. The strategy of multiple oscillation rings isadopted in this work to reduce the size of test set. Next, a theoretical analysis to identify robust untestable path delayfaults is presented. Reconvergence of paths are classified into seven casesand the necessary condition to robustly test path delay faults for each caseis deduced. The proposed procedure is suitable for distributed processing bycircuit partitioning to reduce the computation time and required memory.Experimental results on ISCAS 85' benchmark circuits show that the robustuntestable faults occupy a high percentage. Finally, a functional test pattern generation scheme for obtaining highlyefficient robust tests for path delay faults is presented. The scheme firstanalyzes independent faults that can not be detected in a single pattern pairand then distributes these independent faults into different groups. Thisreduces the number of candidate faults that may be simultaneously detected inthe same pattern pair. The proposed scheme is coded in a vector processingmethodology to reduce computation time and required memory. Experimentalresults demonstrate that our method is fast and the generated pattern pairsare very efficient in detecting path delay faults. Concerning fault simulation, a two-phase fault simulation scheme forsequential circuits is first proposed. In this fault simulation, the faultfree simulation is first performed with few patterns, and then the faultsimulation is performed with the rest of patterns. Five cases of faultswhich result from two- phase fault simulation are discussed in detail.Significant speedup on simulation time can be obtained because this faultsimulation approach can quickly drop Case 1 faults, which are time-consumingfaults and would be considered to be undetectable in the traditionalthree-value fault simulation but are really detected in the exact faultsimulation. Based on the concept of the two-phase fault simulation, distributed faultsimulation by pattern partitioning for sequential circuits is proposed. Thissimulation is done by making each distributed machine perform fault-freesimulation with preceding patterns and then perform fault simulation with itsown patterns. The fault simulation is accelerated since the number ofpatterns needed to be performed fault simulation for each machine is reducedby a factor of n, the number of machines, and the faults detected by anymachine are dropped through communication of the network. A super-linearspeedup can be obtained because this method can also remove the Case 1 faults.