一個測試圖樣平行障礙平行序向邏輯電路障礙模擬硬體加速器之實現

Abstract

本論文,我們實現一個對序向邏輯電路做障礙模擬的硬體加速器的硬體設 計及模擬.此加速器採用了一個障礙模擬演算法以達到測試圖樣平行處理 的能力.另一方面,障礙平行處理能力則是由多個處理器(Processing Element)的技巧來達成.對於細部的架構及硬體設計,我們採用一些獨特的 方法及設計來達成硬體模擬及加速的目標;硬體的模擬是以Verilog硬體描 述語言(Hardware Description Language,HDL)及Compass 0.6u硬體標準 元件庫(Standard Cell Library)來完成.首先我們使用單個處理器,其執 行障礙模擬的處理速度平均可達1.95E+07 G*V/s ~ 8.22E+07 G*V/s.其處 理速度大約是軟體模擬器的20到82倍,當使用到16個處理器時,將再有6.96 倍的加速. In this thesis, we realize the hardware design and circuit simulation of a zero delay fault simulation hardware accelerator for the gate level synchronoussequential circuits. A parallel sequence fault simulation algorithm is used toachieve parallel-pattern fault simulation, and multiple processing elementsare used to achieve the parallel-fault fault simulation. As to detailed architectural and hardware design, we adopt several specific methodologiesand design approaches to fulfill the hardware fault simulation andaccelerate its performance. The proposed architecture is implemented inVerilog hardware description language and targeted for Compass 0.6u cell library. When the accelerator being configured as single PE, its performanceruns at an average from 1.95E+07 G*V/s to 8.22E+07 G* V/s. It's about 20 to 80times of software simulators. A speedup of 6.96 in average can be reached ifit is configured as 16 PEs.