高介電係數夾層LDD N型金氧半元件可靠性設計之探討

Abstract

LDD金氧半場效電晶體以氮化矽與低溫化學氣相沉積氧化層為夾層( spacer)結構已逐漸成為高密度動態隨機存取記憶體設計的一種趨勢。然 而，除了夾層所導致界面狀態的退化外，我們發現此低溫製程將導致元件 額外可靠性的退化。因此，以氮化矽當夾層LDD金氧半元件其熱載子效應 的特性化與壓制是本研究的重點。首先，在這論文中，我們針對使用氮化 矽(Si3N4)當夾層的元件發展出一種能萃取其所產生的氧化層缺陷(包含界 面狀態Nit與氧化層陷阱電荷Qox)的技術。這套技術是根據閘控二極體電 流的量測與閘極造成汲極漏電流的量測。此外，將這技術所求得的氧化層 缺陷與二維數值模擬結合，我們便可得到元件退化的物理微觀現象。基於 實驗的設計，我們設計並製造三種不同中間氧化層(post oxide)結構的測 試元件，研究其熱載子退化與氮化矽夾層下的低溫氧化層之關聯性。我們 發現中間氧化層是形成氧化層陷阱電荷的主要因素，而氧化層陷阱電荷主 導元件的退化。進一步研究可發現因這低溫形成的氧化層品質變差會嚴重 地影響元件的退化特性。因此，我們提出在氮氣中適時的回火來減低氮化 矽夾層下方的氧化層陷阱電荷會有效地抑制熱載子造成的退化。最後，各 種中間氧化層的元件其熱載子可靠性之改善可利用本文建議的氧化層分析 法加以驗証。 LDD MOSFET with silicon nitride spacer and low temperature CVD oxide to form the spacer has been a trend for high density DRAM design. However, our new finding shows that extra degradations of device reliability due to the low temperature process will occur in addition to the spacer induced interface state degradation. Therefore, the characterization and suppression of the hot carrier effects in LDD N-MOSFET devices with silicon nitride spacer will be proposed.In this thesis, first,we developed a characterization technique to profiling these oxide damages (interface states Nit and oxide trapped charges Qox) for devices with silicon-nitride (Si3N4) spacer. It was developed based on the gated-diode current measurement and the GIDL (Gated-Induced-Drain-Leakage) current measurement techniques. By incorporating these determined oxide damages into the two-dimensional numerical simulation, it gives us a physical insight of the device degradation mechanisms. Based on the experimental design, we have designed and fabricated three kinds of tested devices with different post oxide structures to study the correlation between hot carrier degradation and the low temperature oxide underneath the nitride spacer. We found that this post oxide under the Si3N4 spacer is the main factor to induce the amounts of Qox which dominates the device degradation. It further shows that the device degradation will be enhanced due to the poor quality of the low temperature CVD oxide. As a consequence, the reduction of the oxide trapped charges under the nitride spacer will be proposed in this study. Furthermore, it was found that the nitrogen anneal under reasonable time will be effective to suppress the hot carrier induced device degradation. The reasons to improve the hot- carrier reliability for various post-oxide devices have been supported by the proposed oxide damage characterization method.