Full metadata record
DC FieldValueLanguage
dc.contributor.author謝嘉鴻en_US
dc.contributor.authorShieh, Jia-Horngen_US
dc.contributor.author項春申en_US
dc.contributor.authorC. Bernard Shungen_US
dc.date.accessioned2014-12-12T02:17:36Z-
dc.date.available2014-12-12T02:17:36Z-
dc.date.issued1996en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT850428130en_US
dc.identifier.urihttp://hdl.handle.net/11536/62007-
dc.description.abstract在本論文中,實現了一個符合北美數位蜂巢式系統IS-54標準的解碼 及訊號處理單元,此單元主要目的有三:一、錯誤更正:更正訊號傳送中 所造成的錯誤。二、支援呼叫處理:呼叫處理單元所需傳送、接收的資訊 皆通過本單位來達成。三、基頻樞紐:IS-54系統各單元的溝通多透過本 單元來完成。 錯誤更正方面:我們設計了一個省面積的BCH解碼器, 及提出雙向式Viterbi演算法和雙向式無尾式演算法,使用雙向式解碼, 可降低資料槽中帶狀雜訊的干擾,並以低面積方式實現此解碼器,若與單 向式Viterbi相較,只需稍稍改變分支矩陣產生單元及控制單元即可完成 單向 (2, 1, 5)、雙向 (2, 1, 5)與雙向 (4, 1, 5)無尾解碼。 支援 呼叫處理:我們實現了類比控制通道(Analog control channel)與數位傳 輸通道(Digital traffic channel)所需的呼叫處理。 基頻樞紐:實 現了在IS-54系統各單元的溝通,如射頻電路、等化器、語音單元與呼叫 處理單元所需的介面。 為了驗證我們的解碼及訊號處理單元,使用了 可程式化邏輯閘(FPGA)驗證了BCH編碼解碼器、Viterbi 解碼器、IS-54系 統各單元所需的介面...等之類比控制通道、數位傳輸通道的設計。 In this thesis, three major tasts in the digital receiver of the IS-54specifications for the North American Digital Cellular (NADC) mobile phonesystem are investigated: 1) implement error control conding; 2) support callprocessing; and 3) act as the bridge of other modules in the baseband system. In implement error control coding, an {\em area-efficient} BCH decoder, interleaver and majority voting are presented. We also present anarea-efficient Viterbi decoder. The modified bi-directional zero-tailViterbi algorithm and the bi-directional tail-biting Viterbi algorithmare proposed to decoding the convolutional codings in IS-54 system.Comparing with the unidirectional Viterbi decoding, our Viterbiimplementation can apply for unidirectional (2, 1, 5) truncation, zero-tail(2, 1, 5) and tail-biting (4, 1, 5) by only to modified the branch- matricgenerator and the control sequence. Support call processing, we implement the analog control channel (FOCC,RECC) and the associated control channel in digital traffic channel (SACCH,FACCH) for call processing. Act as the bridge of other module, We implement the interface betweenequalizer, RF, speech coder and call processing --- ISA for the IS-54mobile system. For test our implementation in the signal processing and coding for control and traffic channel in IS-54 mobile phone, we use the FPGA toverify the area-efficient BCH decoder, Viterbi decoder, the interface withother modules, the whole analog control channel and part of digital trafficchannel.zh_TW
dc.language.isozh_TWen_US
dc.subject解碼zh_TW
dc.subject訊號處理zh_TW
dc.subject錯誤更正zh_TW
dc.subject雙向式解碼zh_TW
dc.subject數位式蜂巢系統zh_TW
dc.subject行動電話zh_TW
dc.subjectBCHen_US
dc.subjectViterbien_US
dc.subjectconvolutionalen_US
dc.subjectIS-54en_US
dc.subjectsignal processingen_US
dc.subjectmobile phoneen_US
dc.title蜂巢式行動電話中語音及控制模式之解碼及訊號處理zh_TW
dc.titleSignal Processing and Coding for Control and Traffic Channel in IS-54 Mobile Phoneen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis