適用於第三代無線行動通訊之雙模式通道解碼器的設計

Abstract

近年來，由於無線通訊應用的快速成長，前置錯誤更正碼的重要性與日俱增。其中，具有高解碼能力的迴旋碼與渦輪碼皆被廣泛運用。以第三代無線行動通訊標準為例，迴旋碼與渦輪碼同時被規範為其通道解碼器。以硬體實現的觀點而言，為兩者分別設計其專用的解碼器並不經濟。

本論文主旨即在設計一適用於第三代行動通訊標準之雙模式通道解碼器。此設計同時支援最大區塊長度為20,730之渦輪解碼器及不同編碼率的維特比解碼器。其最大資料輸出率分別可達每秒4.52Mb及5.26Mb。為減少外部記憶體的存取次數，我們採用一快取記憶體作為輸入緩衝器。經由有效率的打散器設計，記憶體需求與控制單元複雜度均可有效縮小。本架構以Verilog硬體描述語言撰寫，合成後邏輯閘數大約為11萬5千個。使用0.18um製程實作晶片，晶片面積約11.56mm2，經過儀器量測在100MHz的時脈速度可正常運作，其晶片面積僅11.56mm2。以固定六次迴圈的渦輪碼解碼模式下，平均只需要83mW的功率消耗即可達到標準所規範的最大資料輸出率每秒3.09Mb。

In the recent years, forward error correction schemes is rising and flourishing due to widespread increase of wireless communication applications. Among these standards, turbo codes and convolutional codes are usually adopted at the same time because of their high error correcting ability. However, to design the hardware functional block for each decoder is inefficient. In this thesis, a unified turbo and Viterbi decoder architecture for 3GPP2 standard is presented. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various code rates are implemented to provide maximum data rate of 4.52Mb/s and 5.26Mb/s respectively at a clock rate of 100MHz. The memory access is reduced by the input caching scheme, and the system complexity is lowered by the efficient interleaver design. This chip is fabricated in a 0.18 □m six-metal standard CMOS process. The chip die size is 3.4 x 3.4 mm2 with the core size of 2.7 x 2.7 mm2. It contains 115k gates excluding the embedded memory. The measured power dissipation is 83mW while working at the clock rate of 66MHz to decode a 3.1Mb/s turbo encoded data stream with six iterations.