以記憶體為基礎的高效率可變長度編解碼處理器之設計

Abstract

近年來，隨著多媒體領域的廣泛推廣，造成傳輸頻道的傳輸率（頻 寬）需求上產生一些瓶頸，無法達到很好的即時傳輸效果，例如：遠距教 學、線上會議等。傳輸技術的發展，無法跟得上應用上所須，而且傳輸媒 介有其先天上特性之限制，因此，致使多媒體領域無法把最佳的效果顯現 出來。既然傳輸頻道有其先天上之限制，我們可以使用資料壓縮及解壓縮 的技術，達到利用有限的頻道資源來傳送更多的資料的目的。因此，如何 針對資料壓縮之演算法及硬體架構的實現上作有效的改善及處理，成為一 個重要的課題。在考量運算量複雜度及穩定度等因素下，尤以可變長度編 解碼演算法被廣泛利用，在許多資料壓縮的國際標準中，它已成為必備的 一個處理過程（例如：JPEG, MPEG II, H.263等）。 本論文針對可 變長度編解碼提出新一代的以樹狀搜尋為基礎的演算法，配合內嵌式記憶 體模組，存取相對應的編碼表，並且在硬體架構設計上，作了有效切割， 以緊密配合編解碼的運算步驟，獲得令人激賞的結果。在工作頻率，編碼 表大小及壓縮比例與發表過之相關文獻相等的前提下，本論文所提出之演 算法打破了樹狀資料結構搜尋動作上的依序關係，同時在編碼及解碼的運 算步驟中，所須使用之記憶體空間可以減少約20%∼40%，視編碼表之特性 及大小而定，編碼表越大，本論文之方法可以獲得更多的節省，記憶體空 間之縮小，代表佈局面積縮小，成本降低及速度提升等，這項優點解決了 許多應用層面上所面臨的困擾，而輸出率則是過去提出方法的4∼5倍。 本論文把編碼及解碼系統合成一個整合之系統，利用TSMC 0.6um CMOS 的 製程技術，實現此系統晶片。經驗證可以在100 MHz工作頻率及3V電壓源 環境下運作，假設在256樣本之編碼表及壓縮比例為50% 的運作下，編解 碼輸出率可高達400Mbps。這樣的結果，將足以供給高速及大量資料量傳 輸的應用所須，解決過去一直無法突破的瓶頸。 Recently, the development of multimedia and communication techniques has changed our life style. Meanwhile, the transmitted information has been growing up rapidly. The transmission channel has its physical bandwidth limitation. As a result, the bottleneck of real-time applications is the transmitted bandwidth, such as distance learning , video conference, etc. A simple and efficient method of solving this problem is to use data compression techniques. The development of compression algorithm and architecture becomes important. Variable length coding is the most popular data compression technique which has been used in many data compression standard such as JPEG, MPEG-2, and H.263. In this thesis, we present a new memory-based tree search algorithm and VLSI architecture for VLC/VLD codec system design. Different coding tables can be stored by changing the contents of the memory, without changing the system. The coding table is mapped onto a memory whose space has been minimized by using new tree data structure and efficient mapping procedure. We can reduce about 20% ~ 40% memory space requirement compared with traditional proposed algorithm [8], [9]. In addition, we break the recursive dependency of the iteration searching operations. The system architecture can predict the searching node and perform parallel operations. As a a result, the system throughput rate can be enhanced to about 4 ~ 5 times than previous announced architectures. The proposed architecture mainly consists of memory and simple arithmetic unit which is very suitable for VLSI implementation. We use TSMC 0.6um CMOS technology to implement the single-chip codec system. The codec system can operate at 3V power supply with clock rate up to 100MHz. Assuming 50% compression ratio and 256-entry coding table, the codec system can achieve compression and decompression rate of 400Mbits/s, which implies that the bottleneck of the real-time applications can be solved.