FET推挽式倍頻器之設計

Abstract

本論文設計和量測一個寬頻帶推挽式倍頻器。倍頻器由一個雙面微帶線 巴倫和直接接在平衡端口的兩個Ｂ類放大器組成。平衡式的結構提供內在 的基頻分量壓制。為了減小轉換損失，電路中不包含匹配電路。量測結果 顯示輸出端偏壓電路使用集總電容與電感線圈在倍頻輸出頻率 8-15GHz內 ，有2dB到5dB的轉換損失。輸出端使用微帶傳輸線偏壓電路在倍頻 輸出 頻率 8-15GHz內，有2dB到4dB的轉換損失。 In this thesis, a broadband push-pull frequency doubler is designed and measured. The doubler consists of a microstrip to parallel plate balun and a pair of class B amplifiers. The balanced line is connected to the gate of the amplifier. The balanced structure offers inherent suppression of the fundamental frequency. In order to get broader bandwidth, no matching circuits were used to minimize conversion loss. The doubler utilized lumped capacitor and air-core inductor as output bias circuit shows a conversion loss between 2 dB to 5 dB over an output frequency range of 8-15GHz. The other doubler utilized microstrip as output bias curcuit shows a conversion loss between 2 dB to 4dB over an output frequency range of 8-15GHz.