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dc.contributor.authorChao, Mango C. -T.en_US
dc.contributor.authorCheng, Kwang-Tingen_US
dc.contributor.authorWang, Seongmoonen_US
dc.contributor.authorChakradhar, Srimat T.en_US
dc.contributor.authorEi, Wen-Long V.en_US
dc.date.accessioned2014-12-08T15:07:55Z-
dc.date.available2014-12-08T15:07:55Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-1381-2en_US
dc.identifier.issn1063-6757en_US
dc.identifier.urihttp://hdl.handle.net/11536/6246-
dc.description.abstractThis paper presents a hybrid compaction scheme for test responses containing unknown values, which consists of a space compactor and an unknown-blocking Multiple Input Signature Registers (MISR). The proposed scheme guarantees no coverage loss for the modeled faults. The proposed hybrid scheme can also be tuned to observe any user-specified percentage of responses for controlling the coverage loss for un-modeled faults. The experimental results demonstrate that, in comparison with a space compactor or an unknown-blocking MISR alone, the hybrid compaction scheme achieves a lower coverage loss without demanding more test-data volume. In addition, we propose a quantitative approach to estimate the required percentage of observable responses for the proposed scheme, directly based on a test-quality metric of un-modeled faults.en_US
dc.language.isoen_USen_US
dc.titleA hybrid scheme for compacting test responses with unknown valuesen_US
dc.typeArticleen_US
dc.identifier.journalIEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2en_US
dc.citation.spage513en_US
dc.citation.epage519en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000253303700082-
顯示於類別:會議論文