標題: Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation
作者: Tsai, Hui-Wen
Ker, Ming-Dou
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-一月-2010
摘要: A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-mu m CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCl-X compatible applications. (C) 2009 Elsevier Ltd. All rights reserved.
URI: http://dx.doi.org/10.1016/j.microrel.2009.09.004
http://hdl.handle.net/11536/6273
ISSN: 0026-2714
DOI: 10.1016/j.microrel.2009.09.004
期刊: MICROELECTRONICS RELIABILITY
Volume: 50
Issue: 1
起始頁: 48
結束頁: 56
顯示於類別:期刊論文


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