新型靜態與動態雙載子互補式金氧半邏輯電路之設計與分析及其在低電壓超大型積體電路之應用

Abstract

雙載子互補式金氧半技術結合了互補式金氧半電晶體的高密度、低功率消 耗與雙載子電晶體高驅動能力等優點，使得雙載子互補式金氧半電路適合 運用於超大型積體電路系統中。本論文提出幾個可應用於低電壓超大型積 體電路之新型靜態與動態雙載子互補式金氧半邏輯電路。新開發之邏輯電 路包括多射極雙載子互補式金氧半靜態邏輯及其改良電路、推挽式雙載子 互補式金氧半靜態邏輯及其改良電路、交叉偶合式雙載子互補式金氧半靜 態差動邏輯及其改良電路、鎖存式雙載子互補式金氧半動態邏輯及其改良 電路。首先，本論文提出新型多射極雙載子互補式金氧半邏輯，在此邏輯 電路中運用了兩種電路技術使其在低電壓與複雜邏輯狀態下，仍具有高速 的特性。首先利用多射極雙載子電晶體作為輸入邏輯單元並結合一新型輸 入電路架構來改善傳統雙載子互補式金氧半邏輯電路在複雜邏輯狀態下， 操作速度嚴重減低的問題。接著運用雙載子電晶體基極射極接面寄生電容 耦合效應而使其在2伏特工作電壓下具有高速近完整電位幅度，因而解決 了在低電壓操作時電位幅度損失的問題。其改良電路利用電容耦合效應而 使得其工作電壓降至1.2伏特時仍具有高速近完整電位幅度。推挽式雙載 子互補式金氧半邏輯電路根據電容耦合效應可推高電位的原理，利用電容 使得輸出雙載子電晶體的基極電位因電容耦合效應而提高，同時使得輸出 端對外部負載充電時具有高速完整電位幅度。另一方面利用新型電路架構 並結合電容耦合效應，可有效縮短輸出端放電雙載子電晶體的導通延遲時 間，並且提升輸出端放電速度。因推挽式雙載子互補式金氧半邏輯需要兩 個電容來完成上述功能，故所需晶片面積較大。而其改良電路僅需一個電 容亦可完成上述功能，故解決晶片面積較大的問題。交叉偶合式雙載子互 補式金氧半差動邏輯乃結合傳送電晶體差動邏輯與新型雙載子互補式金氧 半差動緩衝器製作於同一閘中，可提高驅動能力與速度，同時亦解決了傳 統互補式傳送電晶體差動邏輯在低電壓狀態下，因邏輯單元源極電位幅度 損失而造成操作速度嚴重減低的問題。而其改良電路運用交叉偶合的電路 技術，僅需一個電容即可使兩差動輸出端具有高速近完整電位幅度的特性 ，因而提升在1.5伏特電壓下的操作速度。鎖存式雙載子互補式金氧半邏 輯乃結合邏輯閘與鎖存器製作於同一閘中，可減少所需之元件數目。利用 寄生電容耦合效應，使其具有高速近完整電位幅度，並且改善操作速度。 鎖存式雙載子互補式金氧半邏輯及其改良電路，均可應用在真單相時脈管 流系統，因此適用於高速低電壓之超大型積體電路之系統設計。最後，利 用交叉偶合式雙載子互補式金氧半差動邏輯設計加法器作為應用說明。本 論文提出之新型雙載子互補式金氧半邏輯電路，均可應用於高速低電壓之 超大型積體電路，經由實驗晶片之設計、量測，新型邏輯電路的部分特性 與優點得以驗證。本論文提出之新型電路具有上述諸多優點，所以在高速 低電壓之超大型積體電路系統中，具有高度的應用價值及發展潛力。 In this thesis, four new static BiCMOS logic circuits, three new static BiCMOSdifferential logic circuits, six new dynamic BiCMOS/BiNMOS/BiPMOS logic circuits,and three new dynamic BiCMOS/BiNMOS latch logic circuits for low-voltage applications, are proposed and analyzed.First of all, new static BiCMOS logic circuits called the bipolar bootstrapped multi-emitter BiCMOS (B2M-BiCMOS) logic and bootstrapped multi-emitter BiCMOS (BM- BiCMOS) logic are proposed. The proposed new BiCMOS logic circuits do not have DC power dissipation and have near-full- swing output voltage. For complex logic, the compactmulti- emitter structure and a new circuit configuration are proposed as the input logic units in the pull-up and pull-down sections of the proposed BiCMOS logic circuits to achieve the high speed operation, respectively. Moreover, a new bipolar bootstrapping technique and the capacitor bootstrapping technique are adopted in the B2M-BiCMOS logic and the BM-BiCMOS logic to achieve fast near-full-swing operation for 2V and 1.2V supply voltage, respectively. It has been shown that the developed new BiCMOS logic circuits have certain advantages in speed, power dissipation, and chip area over other BiCMOS logic circuits, especially for complex logic.In order to enhance the pull-down speed of the conventional bootstrapped BiCMOS logic circuits under low-voltage operation, new full-swing BiCMOS logic circuits called push-pull bootstrapped BiCMOS (P2B-BiCMOS) and modified push-pull bootstrapped BiCMOS (MP2B-BiCMOS) logics are proposed. These two new BiCMOS logic circuits utilize bootstrapping technique to enhance both pull-up and pull-down switching speed under low-voltage condition. Moreover, the proposed MP2B-BiCMOS logic utilizes a new bootstrapping technique which uses only one bootstrapping capacitor to achieve both fast near full-swing and fast switching operations during pull-up and pull-down periods,respectively, at 1.2V supply voltage.A new BiCMOS differential logic circuits called differential cross-coupled bootstrapped BiCMOS (DC2B-BiCMOS) and differential cross-coupled BiCMOS (DC2-BiCMOS) logic are proposed. The two new logic circuits utilize a novel cross- coupled BiCMOS circuit structure to solve the low regeneration capability problem of PMOS cross-coupled latch in the CMOS CPL circuit and BiCMOS CPL circuits. Moreover, the proposed DC2B- BiCMOS logic utilizes a new cross-coupled bootstrapped technique which uses only one bootstrapping capacitor to achieve fast near full-swing operation for two differential outputs. The speed advantage over other BiCMOS differential logic circuits has been verified by both simulation and experimental results at 1.5V supply voltage.For the true-single-phase pipelined systems, six new true-single-phase-clocking (TSPC) dynamic BiCMOS/BiNMOS/ BiPMOS logic circuits and three new dynamic latch logic circuits for high-speed low-voltage dynamic pipelined system applications are proposed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The proposed CHE-BiCMOS/BiNMOS, CLE-BiCMOS/BiNMOS, CLE-BiPMOS, and CLEPH-BiCMOS dynamic logic circuits can be cascaded directly to form the BiCMOS domino circuit systems. Moreover, the CHE- BiCMOS/BiNMOS, CLE-BiPMOS, and CLEPH-BiCMOS dynamic logic circuits can be combined with CHE-BiCMOS dynamic latch logic, CLE-BiCMOS/BiNMOS dynamic latch logic, and CMOS precharged dynamic circuits to form the true-single-phase BiCMOS pipelined systems. Directly cascadable with CMOS dynamic circuits makes the BiCMOS pipelined system more flexible in delay with different capacitive load and achieving the optimal performance. A 1.5V 32-bit adder is designed by using the CMOS CPL and the new BiCMOS differential logic circuits. In the 32-bit adder, for lower power dissipation operation, the DC2-BiPMOS logic gates are used to generate propagate signal and generate signal, group propagate signal, group carry signal, and sum signal of the critical path to achieve optimal performance. The group generate circuit, and section carry bypass circuit are implementedby using DC2B-BiCMOS logic gates. For the purpose of saving power dissipation, the CMOS CPL circuits are used to implement the other logic gates which are not related to the critical path. This adder shows a speed advantage over the CMOS CPL adder at 1.5V supply voltage.Several experimental chips of the proposed new BiCMOS logic circuits have been designed and fabricated. The measured results are consistent with HSPICE simulation results. Therefore, the proposed static and dynamic BiCMOS logic circuits are suitable for high-speed low-voltage digital VLSI applications.