标题: | New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process |
作者: | Ker, Ming-Dou Chen, Wen-Yi Shieh, Wuu-Trong Wei, I-Ju 电机学院 College of Electrical and Computer Engineering |
关键字: | Ballast resistance;electrostatic discharge (ESD);ESD protection;input/output (I/O) buffer;silicidation |
公开日期: | 1-十二月-2009 |
摘要: | Silicidation has been reported to result in substantial negative impact on the electrostatic discharge (ESD) robustness of MOS field-effect transistors. Although silicide blocking (SB) is a useful method to alleviate ESD degradation from silicidation, it requires additional mask and process steps to somehow increase the fabrication cost. In this paper, two new ballasting layout schemes to effectively improve the ESD robustness of input/output (I/O) buffers with fully silicided NMOS and PMOS transistors have been proposed. Ballasting technique in layout is a cost-effective method to enhance the ESD robustness of fully silicided devices. Experimental results from real IC products have confirmed that the new ballasting layout schemes can successfully increase the HBM ESD robustness of fully silicided I/O buffers from the original 1.5 kV to over 6 kV without using the additional SB mask. |
URI: | http://dx.doi.org/10.1109/TED.2009.2031003 http://hdl.handle.net/11536/6338 |
ISSN: | 0018-9383 |
DOI: | 10.1109/TED.2009.2031003 |
期刊: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 56 |
Issue: | 12 |
起始页: | 3149 |
结束页: | 3159 |
显示于类别: | Articles |
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