金屬化製程對分離式閘極快閃記憶體抹除特性之影響

Abstract

快閃(非揮發性)記憶元件之特性及效能取決於多項製程，尤其在前段製程中與元件相關的部分更是重要，其效能的評估主要為快速寫入及抹除，低功率消耗，長資料儲存時效與耐力等要素，本文所引用之的分離式閘極快閃(非揮發性)記憶元件，雖比傳統堆疊架構式面積大，但是在寫入電壓，電流，效率及過度抹除等特性上則較之為優異。 一般對快閃記憶體甚之研究甚少提及後段製程對其之影響，本文乃針對金屬化製程對快閃記憶體於抹除特性之影響做研究，利用製程監控測試(PCM)，電路功能良率測試(Circuitry function yield test)，除錯電性故障分析(Debug, EFA)，再配合電路佈線(Layout)之特性做系統化分析，而達到改善良率之最終目的。 在本實驗中，由於在不同的濺鍍機台所鍍上之金屬層1的晶圓，在良率測試結果上，會導致不同的抹除(Erase)失敗率，金屬層1是由三明治結構的氮化鈦，鋁銅以及氮化鈦所組成，其中氮化鈦在濺鍍前，會於氬的環境下先鍍上一層富含鈦(Ti-rich)層，再通入氮氣以形成氮化鈦，實驗針對富含鈦層的厚度做分析。 當富含鈦層的厚度較厚時，會得到較低的抹除電流(IR1)，同時對快閃記憶體元件的懸浮閘極與控制閘極的啟始電壓也都會相對偏高，其順向穿隧電壓也比較高，從這些現象可觀察到，較厚的富含鈦層會造成快閃記憶體在抹除特性上不良的影響，此現象也可以從電性故障分析所得到的位元晶胞電流(bit cell current)分佈中得到驗證，較厚的富含鈦層會導致整個快閃記憶體區塊電流分佈大幅下降，而造成抹除失敗。這是由於對記憶體元件的矽與二氧化矽介面中含有許多的懸浮鍵，氫離子在後續的製程中，會進入其中而將其鈍化，達到元件穩定之作用，但較厚的富含鈦層會與更多氫離子反應成為氫化鈦，而造成元件電流偏低的現象。 在實驗中也發現，較厚的富含鈦層會導致金屬層電阻值升高，這是由於當鈦濺鍍於鋁銅合金上時，鈦和鋁發生了合金反應，形成鈦化鋁，其電阻率較鋁為高，因此導致整體電阻的升高，由於位元線是以金屬層1做佈線，較高的電阻率會導致電流的衰減，再加上前段的元件電流偏低現象，更使得位於特定位元線的晶胞易於抹除失敗。 由分析結果可得知，欲得到最佳的抹除特性，富含鈦層必須控制在110 埃(Å)以下。

The characteristics and performance of flash (non-volatile) memory depend on many process stages, especially for flash cell formation related process which belong to front-end process among embedded flash CMOS compatible process flow. It’s evaluation includes fast program and erase, low power consumption, long data retention and high endurance. Although the split gate flash structure we use in this study is larger than traditional stacked gate flash in dimension, the program voltage, current, efficiency and over-erase characteristic performance are better than it. There are few researches that mention about back-end process on flash performance influence. Most of studies are front-end process related. Our study here is to find the metallization effect on flash erase characteristics. We use PCM(Process Control Monitor) test on device level, circuitry function test(yield test), debug function (Electrical Failure Analysis, EFA) and combined with layout study to summary it’s effect. Finally, to improve the flash yield performance is our goal. In our study, due to wafers that their metal_1 sputtered with different machine would result in different erase failure rate in circuitry function test. We split the Ti-rich thickness that is sputtered before TiN layer under pure Ar ambient. In PCM test, thicker Ti-rich layer would induce lower IR1(erased cell current), higher threshold voltage of floating gate and control gate channel and higher forward tunneling voltage. This means the erase performance is worse with thicker Ti-rich layer. From BCC(bit cell current) distribution study, the current of whole flash block is degraded with thicker Ti-rich layer. This is due to dangling bond between Si and SiO2 passivation effect is reduced by thicker Ti-rich because the hydrogen produced either during plasma or anneal process would react with titanium film to form Ti-Hx compound. Therefore, less hydrogen passivate the dangling bonds induce lower surface current of flash cell. In this study, we also found the metal resistivity getting higher with thicker Ti-rich. This is due to Titanim-Aluminide(Al3Ti) formation when Ti-rich been sputtered upon Al layer. The resistivity of Al3Ti is 3 times higher than that of Al. The bit-line of flash IP is made of metal_1, higher resistivity would induce cell current degradation. Combined with passivation effect mentioned above, flash erase failure tend to occur on specific bit-line. In sum, the flash erase performance can be optimized as the Ti-rich layer thickness was kept below 110 Å.