基板材料對於堆疊式快閃記憶體寫入/抹除效率的影響

Abstract

在半導體市場上，快閃記憶體因為不隨電源關閉而遺失資料的特性，近年來在可攜帶式商業產品上有了爆炸性的成長。各種元件尺寸隨著半導體世代而快速的微縮，但對於快閃記憶體而言，提供載子穿隧的氧化層若為了提高寫入/抹除速度而降低厚度，則會降低資料保存的期限，同時因為尺寸的微縮，即便是少量載子的損失，就會造成讀取資料時發生錯誤。從研究文獻得知，最適當的穿隧氧化層厚度約為8至11奈米。除非在元件結構、材料、或者操作機制上有所改變，否則無法改變目前快閃記憶體所面臨的窘境。近來鍺相關的半導體元件，因為較小的等效電子、電洞質量，而使得操作速度獲得了有效的提升。同時相較於矽基板，鍺基板擁有更為強烈因衝擊而游離產生電子、電洞對的效應，這使我們好奇是否將鍺材料應用於快閃記憶體，也同樣可以得到明顯的好處。 我們應用了軟體ISE TCAD，來達成元件模擬的目的。由於該軟體是預設矽為主要製程、元件模擬對象，所以在進行模擬前，我們嘗試找出所有可以更改的參數，同時配合文獻中所提供的矽、鍺數學模型，來確保模擬結果的正確性。我們列出了所使用的數學模型包含: 能帶模型、電致漂移率模型、衝擊離子化率模型、熱導模型、流體動力學模型、電容耦合模型;以及在寫入/抹除快閃記憶體時運用到的物理機制:F-N穿隧機制、及熱載子穿隧機制。由於該軟體尚未提供鍺相關的製程模擬，所以我們僅藉由畫出元件結構後，再進行元件模擬。 我們利用通道熱電子穿隧以及F-N穿隧至浮閘的觀念分別寫入快閃記憶體;利用了F-N穿隧的概念，來進行記憶體的抹除。從通道熱電子穿隧寫入的模擬結果發現，由於控制閘極耦合電容的影響，加上電位移向量在半導體-氧化層界面連續的觀念，擁有較高介電常數的鍺反而得到較小的等效電場，決定了穿隧電流反倒是不如矽基板;在F-N穿隧寫入的模擬中，即便鍺基板擁有較大的總耦合電容，使得在浮閘的耦合電壓大於矽基板，但仍舊是半導體-氧化層界面的電場扮演了穿隧電流的決定性因素，得到的結果仍舊是矽基板的寫入速度高於鍺基板;在F-N抹除的模擬中，運用與F-N寫入相同的數學模型，仍舊看見在鍺基板上未能得到速度上的改善，同時用數學的計算展示了合理的解釋。 最後，我們提出了對於研究結果的簡單結論。同時對於模擬而言，最重要的還是需要實驗結果來驗證其正確性，並建立有效快速預測結果的數學型式，來省去大量的晶片耗損。最後列出了幾點將來研究的方向，以及尚需解決的問題。

A large amount of semiconductor markets are given by the semiconductor memories. The past decade in the field of Flash memories have been the explosive growth, driven by cellular phones and other portable equipments. In order to improve the speed of Flash cell, it is necessary to lower the tunneling oxide (TOX) thickness. However, this causes the loss of charges at the same time. According to the trade-off between speed and reliability, the thickness of TOX is compromised to about 8-11nm. Unless changing of device structures, materials, and operating mechanisms, we can’t overcome the difficulty which Flash memories meet. Recently, germanium (Ge) has prompted renewed interest in Ge-based devices due to the lower effective mass and higher mobility of carriers in Ge as compared to silicon (Si). Ge also exhibits more serious impact ionization which is responsible for channel hot electrons (CHE) injection programming. We think the differences of Si and Ge in physical characteristics may change the operating mechanisms, and bring some solutions to improve programming/erasing efficiency of Flash memories. We use ISE TACD for our simulate work. The tool has set Si-related process and device simulation parameters as default. We have changed the parameters what we could found, basing on the published papers and books to make sure the simulate results. The models are: energy band model, mobility model, impact ionization rate model, thermal conductivity model, hydrodynamic model, and capacitive coupling model. The mechanisms are: Fowler-Nordheim (F-N) tunneling and hot carriers injection. All of the results are just gotten from device simulation but without process simulation since ISE still has no Ge-related process simulation. We use CHE and channel F-N (CFN) to program the Flash cells respectively, and use F-N tunneling to erase the Flash cells. On CHE programming, the higher coupling ratio of control-gate (CG) makes the higher electrical field across TOX in Si than Ge. Also because of the continuity of displacement vector, the higher permittivity of Ge would cause the lower electrical field at interface. We get the higher gate current in Si than Ge. On CFN programming, the higher CT in Ge would show the higher electrical field across TOX. However, the parameters of F-N tunneling are calculated and showing the gate current in Si is larger than Ge. On the same mechanism of F-N tunneling erasing, the parameters also show the higher electrical filed (Einj) of Si would cause the higher erasing speed. The continuity of displacement vector also explains the higher electrical field at interface for F-N tunneling programming/erasing. Finally, we show the simple conclusions for our research. The simulate characteristics always need the experimental results to prove the correctness, and build the mathematical model. We also show recommendations for the future works.